[PATCH] D14588: [X86][SSE] Transform truncation from v8i32/v16i32 to v8i8/v16i8 into bitand and X86ISD::PACKUS operations during DAG combine.

[Simon Pilgrim via llvm-commits]

RKSimon added a comment.

I've added the current codegen to the vector-trunc.ll tests for comparison so please can you rebase against that?

I wonder if it would be better to combine to bitcast/shuffle pairs instead of specific X86ISD nodes? And then focus on improving the existing shuffle lowering with PACKUS (e.g. I don't think we're making use of PACKUSDW at all yet).


http://reviews.llvm.org/D14588