[PATCH] D14489: [AArch64] Applying load pair optimization for volatile load/store

[Junmo Park via llvm-commits]

flyingforyou added a comment.

Hi Chad.

Could you give me an idea that how to change the code without limiting scan value to 1?

Should I make another function for merging adjacent volatile ldr/str?

Or move  "hasOrderedMemoryRef" function to inside of "findMatchingInsn" and 
change the Limit value 1 if the first instruction is volatile.

First one makes many duplication of codes. You may not be satisfied with second one.
If you have any other opinion, tell me please.

Thanks.


http://reviews.llvm.org/D14489