[PATCH] D14557: Assume lane masks are precise

[Matthias Braun via llvm-commits]

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Assuming I get no complains in the E-Mail thread (http://lists.llvm.org/pipermail/llvm-dev/2015-November/092238.html) lane masks should be changed to be precise.

Allowing imprecise lane masks in case of more than 32 sub register lanes
lead to some tricky corner cases, and I need another bugfix for another
one. Instead I rather declare lane masks as precise and let tablegen
abort if we do not have enough bits.

This does not affect any in-tree target, even AMDGPU only needs 16 lanes
at the moment. If the 32 lanes turn out to be a problem in the future,
then we can easily change the LaneBitmask typedef to uint64_t.

Repository:
  rL LLVM

http://reviews.llvm.org/D14557

Files:
  include/llvm/Target/TargetRegisterInfo.h
  lib/CodeGen/RegisterCoalescer.cpp
  lib/CodeGen/VirtRegMap.cpp
  utils/TableGen/CodeGenRegisters.cpp

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