[llvm] r252555 - [Hexagon] Fixing load instruction parsing and reenabling tests.
Colin LeMahieu via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 9 16:02:27 PST 2015
Author: colinl
Date: Mon Nov 9 18:02:27 2015
New Revision: 252555
URL: http://llvm.org/viewvc/llvm-project?rev=252555&view=rev
Log:
[Hexagon] Fixing load instruction parsing and reenabling tests.
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h
llvm/trunk/test/CodeGen/Hexagon/always-ext.ll
llvm/trunk/test/CodeGen/Hexagon/static.ll
llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt
llvm/trunk/test/MC/Hexagon/instructions/ld.s
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td?rev=252555&r1=252554&r2=252555&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td Mon Nov 9 18:02:27 2015
@@ -3631,9 +3631,9 @@ let AddedComplexity = 100 in {
//===----------------------------------------------------------------------===//
let isPredicable = 1, hasSideEffects = 0 in
class T_LoadAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
- bits<3> MajOp, Operand AddrOp, bit isAbs>
- : LDInst <(outs RC:$dst), (ins AddrOp:$addr),
- "$dst = "#mnemonic# !if(isAbs, "(##", "(#")#"$addr)",
+ bits<3> MajOp>
+ : LDInst <(outs RC:$dst), (ins ImmOp:$addr),
+ "$dst = "#mnemonic# "(#$addr)",
[], "", V2LDST_tc_ld_SLOT01> {
bits<5> dst;
bits<19> addr;
@@ -3658,7 +3658,7 @@ class T_LoadAbsGP <string mnemonic, Regi
class T_LoadAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
bits<3> MajOp>
- : T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp, u32Imm, 1>, AddrModeRel {
+ : T_LoadAbsGP <mnemonic, RC, u32MustExt, MajOp>, AddrModeRel {
string ImmOpStr = !cast<string>(ImmOp);
let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
@@ -3676,10 +3676,11 @@ class T_LoadAbs <string mnemonic, Regist
// Template class for predicated load instructions with
// absolute addressing mode.
//===----------------------------------------------------------------------===//
-let isPredicated = 1, opExtentBits = 6, opExtendable = 2 in
+let isPredicated = 1, hasSideEffects = 0, hasNewValue = 1, opExtentBits = 6,
+ opExtendable = 2 in
class T_LoadAbs_Pred <string mnemonic, RegisterClass RC, bits<3> MajOp,
bit isPredNot, bit isPredNew>
- : LDInst <(outs RC:$dst), (ins PredRegs:$src1, u6Ext:$absaddr),
+ : LDInst <(outs RC:$dst), (ins PredRegs:$src1, u32MustExt:$absaddr),
!if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#"$dst = "#mnemonic#"(#$absaddr)">, AddrModeRel {
bits<5> dst;
@@ -3753,7 +3754,7 @@ defm loadrd : LD_Abs<"memd", "LDrid",
let isAsmParserOnly = 1 in
class T_LoadGP <string mnemonic, string BaseOp, RegisterClass RC, Operand ImmOp,
bits<3> MajOp>
- : T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp, globaladdress, 0>, PredNewRel {
+ : T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp>, PredNewRel {
let BaseOpcode = BaseOp#_abs;
}
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp?rev=252555&r1=252554&r2=252555&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp Mon Nov 9 18:02:27 2015
@@ -60,9 +60,9 @@ void HexagonMCELFStreamer::EmitInstructi
if (Extended) {
if (HexagonMCInstrInfo::isDuplex(*MCII, *MCI)) {
MCInst *SubInst = const_cast<MCInst *>(MCI->getOperand(1).getInst());
- HexagonMCInstrInfo::clampExtended(*MCII, *SubInst);
+ HexagonMCInstrInfo::clampExtended(*MCII, getContext(), *SubInst);
} else {
- HexagonMCInstrInfo::clampExtended(*MCII, *MCI);
+ HexagonMCInstrInfo::clampExtended(*MCII, getContext(), *MCI);
}
Extended = false;
} else {
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp?rev=252555&r1=252554&r2=252555&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp Mon Nov 9 18:02:27 2015
@@ -87,7 +87,8 @@ bool HexagonMCInstrInfo::canonicalizePac
return true;
}
-void HexagonMCInstrInfo::clampExtended(MCInstrInfo const &MCII, MCInst &MCI) {
+void HexagonMCInstrInfo::clampExtended(MCInstrInfo const &MCII,
+ MCContext &Context, MCInst &MCI) {
assert(HexagonMCInstrInfo::isExtendable(MCII, MCI) ||
HexagonMCInstrInfo::isExtended(MCII, MCI));
MCOperand &exOp =
@@ -95,10 +96,10 @@ void HexagonMCInstrInfo::clampExtended(M
// If the extended value is a constant, then use it for the extended and
// for the extender instructions, masking off the lower 6 bits and
// including the assumed bits.
- if (exOp.isImm()) {
+ int64_t Value;
+ if (exOp.getExpr()->evaluateAsAbsolute(Value)) {
unsigned Shift = HexagonMCInstrInfo::getExtentAlignment(MCII, MCI);
- int64_t Bits = exOp.getImm();
- exOp.setImm((Bits & 0x3f) << Shift);
+ exOp.setExpr(MCConstantExpr::create((Value & 0x3f) << Shift, Context));
}
}
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h?rev=252555&r1=252554&r2=252555&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h Mon Nov 9 18:02:27 2015
@@ -67,7 +67,7 @@ bool canonicalizePacket(MCInstrInfo cons
HexagonMCChecker *Checker);
// Clamp off upper 26 bits of extendable operand for emission
-void clampExtended(MCInstrInfo const &MCII, MCInst &MCI);
+void clampExtended(MCInstrInfo const &MCII, MCContext &Context, MCInst &MCI);
// Return the extender for instruction at Index or nullptr if none
MCInst const *extenderForIndex(MCInst const &MCB, size_t Index);
Modified: llvm/trunk/test/CodeGen/Hexagon/always-ext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/always-ext.ll?rev=252555&r1=252554&r2=252555&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/always-ext.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/always-ext.ll Mon Nov 9 18:02:27 2015
@@ -1,5 +1,4 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
-; XFAIL: *
; Check that we don't generate an invalid packet with too many instructions
; due to a store that has a must-extend operand.
Modified: llvm/trunk/test/CodeGen/Hexagon/static.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/static.ll?rev=252555&r1=252554&r2=252555&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/static.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/static.ll Mon Nov 9 18:02:27 2015
@@ -1,5 +1,4 @@
; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-dfa-sched -disable-hexagon-misched < %s | FileCheck %s
-; XFAIL: *
@num = external global i32
@acc = external global i32
Modified: llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt?rev=252555&r1=252554&r2=252555&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt Mon Nov 9 18:02:27 2015
@@ -1,6 +1,5 @@
# RUN: llvm-mc -triple hexagon -disassemble < %s | FileCheck %s
# Hexagon Programmer's Reference Manual 11.5 LD
-# XFAIL: *
# Load doubleword
0x90 0xff 0xd5 0x3a
Modified: llvm/trunk/test/MC/Hexagon/instructions/ld.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/ld.s?rev=252555&r1=252554&r2=252555&view=diff
==============================================================================
--- llvm/trunk/test/MC/Hexagon/instructions/ld.s (original)
+++ llvm/trunk/test/MC/Hexagon/instructions/ld.s Mon Nov 9 18:02:27 2015
@@ -1,12 +1,6 @@
# RUN: llvm-mc -triple hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s
# Hexagon Programmer's Reference Manual 11.5 LD
-# XFAIL: *
-# Load doubleword
-# CHECK: 90 ff d5 3a
-r17:16 = memd(r21 + r31<<#3)
-# CHECK: b0 c2 c0 49
-r17:16 = memd(#168)
# CHECK: 02 40 00 00
# CHECK-NEXT: 10 c5 c0 49
r17:16 = memd(##168)
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