[PATCH] D13956: [x86] try harder to match bitwise 'or' into an LEA

[Sanjay Patel via llvm-commits]

spatel added a comment.

In http://reviews.llvm.org/D13956#285341, @qcolombet wrote:

> One comment though, I believe the problem with isBaseWithConstantOffset is not the use of MaskedValueIsZero, but the fact we expect a constant to feed that mask. I wonder if it could be of general use to refactor the logic so that it is available everywhere, like isOrSameAsAdd or something.


Thanks, Kevin and Quentin. Yes, this is a good point. At the least, we should be able to share the logic with DAGCombiner. It is currently doing this:

  // fold (a+b) -> (a|b) iff a and b share no bits.
  if (VT.isInteger() && !VT.isVector()) {
    APInt LHSZero, LHSOne;
    APInt RHSZero, RHSOne;
    DAG.computeKnownBits(N0, LHSZero, LHSOne);
  
    if (LHSZero.getBoolValue()) {
      DAG.computeKnownBits(N1, RHSZero, RHSOne);
  
      // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
      // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
      if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero){
        if (!LegalOperations || TLI.isOperationLegal(ISD::OR, VT))
          return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1);
      }
    }
  }


http://reviews.llvm.org/D13956