[PATCH] D14397: [mips] Define patterns for the atomic_{load, store}_{8, 16, 32, 64} nodes.

[Vasileios Kalintiris via llvm-commits]

vkalintiris created this revision.
vkalintiris added a reviewer: dsanders.
vkalintiris added a subscriber: llvm-commits.
Herald added a subscriber: dsanders.

Without these patterns we would generate a complete LL/SC sequence.
This would be problematic for memory regions marked as WRITE-only or
READ-only, as the instructions LL/SC would read/write to the protected
memory regions correspondingly.

http://reviews.llvm.org/D14397

Files:
  lib/Target/Mips/Mips64InstrInfo.td
  lib/Target/Mips/MipsISelLowering.cpp
  lib/Target/Mips/MipsInstrInfo.td
  test/CodeGen/Mips/atomic-load-store.ll
  test/CodeGen/Mips/atomicSCr6.ll

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