[llvm] r252008 - AMDGPU: Fix off by one error in register parsing

Matt Arsenault via llvm-commits llvm-commits at lists.llvm.org
Tue Nov 3 14:50:28 PST 2015


Author: arsenm
Date: Tue Nov  3 16:50:27 2015
New Revision: 252008

URL: http://llvm.org/viewvc/llvm-project?rev=252008&view=rev
Log:
AMDGPU: Fix off by one error in register parsing

If trying to use one past the end, this would assert.

Added:
    llvm/trunk/test/MC/AMDGPU/out-of-range-registers.s
Modified:
    llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp?rev=252008&r1=252007&r2=252008&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp Tue Nov  3 16:50:27 2015
@@ -545,11 +545,12 @@ bool AMDGPUAsmParser::ParseRegister(unsi
     }
   }
 
-  const MCRegisterInfo *TRC = getContext().getRegisterInfo();
-  unsigned RC = getRegClass(IsVgpr, RegWidth);
-  if (RegIndexInClass > TRC->getRegClass(RC).getNumRegs())
+  const MCRegisterInfo *TRI = getContext().getRegisterInfo();
+  const MCRegisterClass RC = TRI->getRegClass(getRegClass(IsVgpr, RegWidth));
+  if (RegIndexInClass >= RC.getNumRegs())
     return true;
-  RegNo = TRC->getRegClass(RC).getRegister(RegIndexInClass);
+
+  RegNo = RC.getRegister(RegIndexInClass);
   return false;
 }
 

Added: llvm/trunk/test/MC/AMDGPU/out-of-range-registers.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/out-of-range-registers.s?rev=252008&view=auto
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/out-of-range-registers.s (added)
+++ llvm/trunk/test/MC/AMDGPU/out-of-range-registers.s Tue Nov  3 16:50:27 2015
@@ -0,0 +1,14 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s
+
+s_add_i32 s104, s0, s1
+// CHECK: error: invalid operand for instruction
+
+s_add_i32 s105, s0, s1
+// CHECK: error: invalid operand for instruction
+
+v_add_i32 v256, v0, v1
+// CHECK: error: invalid operand for instruction
+
+v_add_i32 v257, v0, v1
+// CHECK: error: invalid operand for instruction




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