[PATCH] D13633: Type legalizer for masked gather/scatter intrinsics

[Elena Demikhovsky via llvm-commits]

delena added inline comments.

================
Comment at: ../lib/CodeGen/SelectionDAG/LegalizeTypes.h:746-750
@@ -740,5 +745,7 @@
   /// input vector must have the same element type as NVT.
-  SDValue ModifyToType(SDValue InOp, EVT WidenVT);
-
+  /// When FillWithZeroes is "on" the vector will be widened with
+  /// zeroes.
+  /// By default, the vector will be widened with undefined values.
+  SDValue ModifyToType(SDValue InOp, EVT NVT, bool FillWithZeroes = false);
 
   //===--------------------------------------------------------------------===//
----------------
I removed "Slpat". I don't need it.
"Zext" extension is not target specific, at least for the mask.

================
Comment at: ../lib/Target/X86/X86ISelLowering.cpp:11732
@@ -11729,7 +11731,3 @@
 
-    if (IdxVal == OpVT.getVectorNumElements() / 2) {
-      // Zero upper bits of the Vec
-      Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
-      Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
-
+    if (IdxVal == NumElems / 2) {
       SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
----------------
There are the special SHIFT instructions for mask vector KSHIFTR, KSHIFTL (in AVX-512)

When we insert v8i1 into  v16i1, the index should be 8 (I'll add an assertion) or 0.
If v16i1 is allzero, it's enough to shift the input vector left-right.

================
Comment at: ../test/CodeGen/X86/masked_gather_scatter.ll:170
@@ +169,3 @@
+; SKX-NEXT:    kmovw %k1, %k2
+; SKX-NEXT:    vpgatherdd (%rdi,%ymm0,4), %ymm1 {%k2}
+; SKX-NEXT:    vmovaps %zmm1, %zmm2
----------------
The base address in %rdi. (In %edi for 32-bit). In %ymm0 we have only indices. The real address of each element is  "base +index*scale" ->  %rdi + ymm[i] * 4


Repository:
  rL LLVM

http://reviews.llvm.org/D13633