[PATCH] D14214: [X86] DAGCombine should not introduce FILD in soft-float mode

[Michael Kuperstein via llvm-commits]

mkuper created this revision.
mkuper added reviewers: nadav, mbodart.
mkuper added a subscriber: llvm-commits.

The x86 "sitofp i64 to double" dag combine, in 32-bit mode, lowers the sitofp directly to X86ISD::FILD (or FILD_FLAG).
This should not be done in soft-float mode.

http://reviews.llvm.org/D14214

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/soft-sitofp.ll

Index: test/CodeGen/X86/soft-sitofp.ll
===================================================================
--- test/CodeGen/X86/soft-sitofp.ll
+++ test/CodeGen/X86/soft-sitofp.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
+target triple = "i386-pc-linux"
+
+; Function Attrs: nounwind
+; CHECK-LABEL: ll_to_d:
+; CHECK: calll __floatdidf
+define double @ll_to_d(i64 %n) #0 {
+entry:
+  %conv = sitofp i64 %n to double
+  ret double %conv
+}
+
+attributes #0 = { nounwind "use-soft-float"="true" }
Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -26446,8 +26446,8 @@
   }
 
   // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
-  // a 32-bit target where SSE doesn't support i64->FP operations.
-  if (Op0.getOpcode() == ISD::LOAD) {
+  // a 32-bit target where SSE doesn't support i64->FP operations.  
+  if (!Subtarget->useSoftFloat() && Op0.getOpcode() == ISD::LOAD) {
     LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
     EVT LdVT = Ld->getValueType(0);
 


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