[PATCH] D13593: [mips] wrong opcode for ll/sc instructions on mipsr6 when -integrated-as is used
Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 29 07:42:32 PDT 2015
This revision was automatically updated to reflect the committed changes.
Closed by commit rL251629: [mips] wrong opcode for ll/sc instructions on mipsr6 when -integrated-as is used (authored by zjovanovic).
Changed prior to commit:
http://reviews.llvm.org/D13593?vs=38665&id=38737#toc
Repository:
rL LLVM
http://reviews.llvm.org/D13593
Files:
llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
llvm/trunk/test/CodeGen/Mips/atomicSCr6.ll
Index: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
@@ -1329,15 +1329,20 @@
DebugLoc DL = MI->getDebugLoc();
unsigned LL, SC, ZERO, BNE, BEQ;
- if (Size == 4) {
- LL = isMicroMips ? Mips::LL_MM : Mips::LL;
- SC = isMicroMips ? Mips::SC_MM : Mips::SC;
+ if (Size == 4) {
+ if (isMicroMips) {
+ LL = Mips::LL_MM;
+ SC = Mips::SC_MM;
+ } else {
+ LL = Subtarget.hasMips32r6() ? Mips::LL_R6 : Mips::LL;
+ SC = Subtarget.hasMips32r6() ? Mips::SC_R6 : Mips::SC;
+ }
ZERO = Mips::ZERO;
BNE = Mips::BNE;
BEQ = Mips::BEQ;
} else {
- LL = Mips::LLD;
- SC = Mips::SCD;
+ LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
+ SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
ZERO = Mips::ZERO_64;
BNE = Mips::BNE64;
BEQ = Mips::BEQ64;
Index: llvm/trunk/test/CodeGen/Mips/atomicSCr6.ll
===================================================================
--- llvm/trunk/test/CodeGen/Mips/atomicSCr6.ll
+++ llvm/trunk/test/CodeGen/Mips/atomicSCr6.ll
@@ -0,0 +1,32 @@
+; RUN: llc -asm-show-inst -march=mips64el -mcpu=mips64r6 < %s -filetype=asm -o - | FileCheck %s -check-prefix=CHK64
+; RUN: llc -asm-show-inst -march=mipsel -mcpu=mips32r6 < %s -filetype=asm -o -| FileCheck %s -check-prefix=CHK32
+
+define internal i32 @atomic_load_test1() #0 {
+entry:
+
+ %load_add = alloca i32*, align 8
+ %.atomicdst = alloca i32, align 4
+ %0 = load i32*, i32** %load_add, align 8
+ %1 = load atomic i32, i32* %0 acquire, align 4
+ store i32 %1, i32* %.atomicdst, align 4
+ %2 = load i32, i32* %.atomicdst, align 4
+
+ ret i32 %2
+}
+
+define internal i64 @atomic_load_test2() #0 {
+entry:
+
+ %load_add = alloca i64*, align 16
+ %.atomicdst = alloca i64, align 8
+ %0 = load i64*, i64** %load_add, align 16
+ %1 = load atomic i64, i64* %0 acquire, align 8
+ store i64 %1, i64* %.atomicdst, align 8
+ %2 = load i64, i64* %.atomicdst, align 8
+
+ ret i64 %2
+}
+;CHK32: LL_R6
+;CHK32: SC_R6
+;CHK64: LLD_R6
+;CHK64: SCD_R6
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D13593.38737.patch
Type: text/x-patch
Size: 2208 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20151029/e4c29d91/attachment.bin>
More information about the llvm-commits
mailing list