[PATCH] D13700: [Power PC] llvm soft float support for ppc32

[hfinkel@anl.gov via llvm-commits]

hfinkel added inline comments.

================
Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:71
@@ -74,3 +70,3 @@
   addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
-  addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
-  addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
+  if(!Subtarget.useSoftFloat()) {
+    addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
----------------
Add a space after 'if'

================
Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:2948
@@ +2947,3 @@
+
+    if(Subtarget.useSoftFloat())
+       NumFPArgRegs = 0;
----------------
Add a space after 'if'

================
Comment at: lib/Target/PowerPC/PPCTargetMachine.cpp:235
@@ -234,1 +234,3 @@
 
+  bool SoftFloat =
+    F.hasFnAttribute("use-soft-float") &&
----------------
You've copied this code from the ARM and/or X86 targets, but did not copy the associated FIXME comment above it. Please copy the associated FIXME comment as well.

================
Comment at: test/CodeGen/PowerPC/ppcsoftops.ll:50
@@ +49,2 @@
+
+attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc" "target-features"="+soft-float,-altivec,-bpermd,-crypto,-direct-move,-extdiv,-power8-vector,-qpx,-vsx" "unsafe-fp-math"="false" "use-soft-float"="true" }
----------------
Please remove unnecessary attributes.


Repository:
  rL LLVM

http://reviews.llvm.org/D13700