[PATCH] D13593: [mips] wrong opcode for ll/sc instructions on mipsr6 when -integrated-as is used

[Daniel Sanders via llvm-commits]

dsanders requested changes to this revision.
dsanders added a comment.
This revision now requires changes to proceed.

Thanks. This patch is nearly there.

> I will add checks for ll, lld and scd opcodes.


You haven't added these checks yet.


================
Comment at: lib/Target/Mips/MipsISelLowering.cpp:1550
@@ -1514,32 +1549,3 @@
 
-  //  loop2MBB:
-  //    and     maskedoldval1,oldval,mask2
-  //    or      storeval,maskedoldval1,shiftednewval
-  //    sc      success,storeval,0(alignedaddr)
-  //    beq     success,$0,loop1MBB
-  BB = loop2MBB;
-  BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
-    .addReg(OldVal).addReg(Mask2);
-  BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
-    .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
-  unsigned SC = isMicroMips ? Mips::SC_MM : Mips::SC;
-  BuildMI(BB, DL, TII->get(SC), Success)
-      .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
-  BuildMI(BB, DL, TII->get(Mips::BEQ))
-      .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
-
-  //  sinkMBB:
-  //    srl     srlres,maskedoldval0,shiftamt
-  //    sign_extend dest,srlres
-  BB = sinkMBB;
-
-  BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
-      .addReg(MaskedOldVal0).addReg(ShiftAmt);
-  BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
-
-  MI->eraseFromParent();   // The instruction is gone now.
-
-  return exitMBB;
-}
 
 MachineBasicBlock *MipsTargetLowering::emitSEL_D(MachineInstr *MI,
----------------
Nit: Remove unnecessary blank line

================
Comment at: test/CodeGen/Mips/at1.ll:1
@@ +1,2 @@
+; RUN: llc -asm-show-inst  -march=mips64el -mcpu=mips64r6 < %s -filetype=asm -o - \
+; RUN:   | FileCheck %s 
----------------
(about filename): Please rename at1.ll to something meaningful. There are some existing tests named atomic*.ll. Something similar would make sense to me.


http://reviews.llvm.org/D13593