[llvm] r251401 - [ARM] Expand ROTL and ROTR of vector value types

[Charlie Turner via llvm-commits]

Author: chatur01
Date: Tue Oct 27 05:25:20 2015
New Revision: 251401

URL: http://llvm.org/viewvc/llvm-project?rev=251401&view=rev
Log:
[ARM] Expand ROTL and ROTR of vector value types

Summary: After D13851 landed, we saw backend crashes when compiling the reduced test case included in this patch. The right fix seems to be to allow these vector types for expansion in instruction selection.

Reviewers: rengolin, t.p.northover

Subscribers: RKSimon, t.p.northover, aemerson, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D14082

Added:
    llvm/trunk/test/CodeGen/AArch64/rotate.ll
    llvm/trunk/test/CodeGen/ARM/rotate.ll
Modified:
    llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=251401&r1=251400&r2=251401&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Tue Oct 27 05:25:20 2015
@@ -220,6 +220,10 @@ AArch64TargetLowering::AArch64TargetLowe
   // AArch64 lacks both left-rotate and popcount instructions.
   setOperationAction(ISD::ROTL, MVT::i32, Expand);
   setOperationAction(ISD::ROTL, MVT::i64, Expand);
+  for (MVT VT : MVT::vector_valuetypes()) {
+    setOperationAction(ISD::ROTL, VT, Expand);
+    setOperationAction(ISD::ROTR, VT, Expand);
+  }
 
   // AArch64 doesn't have {U|S}MUL_LOHI.
   setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=251401&r1=251400&r2=251401&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Oct 27 05:25:20 2015
@@ -718,7 +718,11 @@ ARMTargetLowering::ARMTargetLowering(con
   }
 
   // ARM does not have ROTL.
-  setOperationAction(ISD::ROTL,  MVT::i32, Expand);
+  setOperationAction(ISD::ROTL, MVT::i32, Expand);
+  for (MVT VT : MVT::vector_valuetypes()) {
+    setOperationAction(ISD::ROTL, VT, Expand);
+    setOperationAction(ISD::ROTR, VT, Expand);
+  }
   setOperationAction(ISD::CTTZ,  MVT::i32, Custom);
   setOperationAction(ISD::CTPOP, MVT::i32, Expand);
   if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())

Added: llvm/trunk/test/CodeGen/AArch64/rotate.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/rotate.ll?rev=251401&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/rotate.ll (added)
+++ llvm/trunk/test/CodeGen/AArch64/rotate.ll Tue Oct 27 05:25:20 2015
@@ -0,0 +1,14 @@
+; RUN: llc < %s -mtriple=aarch64--linux-gnueabihf | FileCheck %s
+
+;; This used to cause a backend crash about not being able to
+;; select ROTL. Make sure if generates the basic ushr/shl.
+define <2 x i64> @testcase(<2 x i64>* %in) {
+; CHECK-LABEL: testcase
+; CHECK: ushr {{v[0-9]+}}.2d
+; CHECK: shl  {{v[0-9]+}}.2d
+  %1 = load <2 x i64>, <2 x i64>* %in
+  %2 = lshr <2 x i64> %1, <i64 8, i64 8>
+  %3 = shl <2 x i64> %1, <i64 56, i64 56>
+  %4 = or <2 x i64> %2, %3
+  ret <2 x i64> %4
+}

Added: llvm/trunk/test/CodeGen/ARM/rotate.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/rotate.ll?rev=251401&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/rotate.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/rotate.ll Tue Oct 27 05:25:20 2015
@@ -0,0 +1,14 @@
+; RUN: llc < %s -mtriple=thumbv8--linux-gnueabihf | FileCheck %s
+
+;; This used to cause a backend crash about not being able to
+;; select ROTL. Make sure if generates the basic VSHL/VSHR.
+define <2 x i64> @testcase(<2 x i64>* %in) {
+; CHECK-LABEL: testcase
+; CHECK: vshl.i64
+; CHECK: vshr.u64
+  %1 = load <2 x i64>, <2 x i64>* %in
+  %2 = lshr <2 x i64> %1, <i64 8, i64 8>
+  %3 = shl <2 x i64> %1, <i64 56, i64 56>
+  %4 = or <2 x i64> %2, %3
+  ret <2 x i64> %4
+}