[PATCH] D14093: AMDGPU: Disallow flat_scr in SI assembler

[Matt Arsenault via llvm-commits]

arsenm created this revision.
arsenm added a reviewer: tstellarAMD.
arsenm added a subscriber: llvm-commits.
Herald added a subscriber: arsenm.

http://reviews.llvm.org/D14093

Files:
  lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
  test/MC/AMDGPU/flat-scratch.s

Index: test/MC/AMDGPU/flat-scratch.s
===================================================================
--- /dev/null
+++ test/MC/AMDGPU/flat-scratch.s
@@ -0,0 +1,28 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=SI %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=CI %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=VI %s
+
+s_mov_b64 flat_scr, -1
+// SI: error: invalid operand for instruction
+// CI-NOT: error
+// VI-NOT: error
+
+s_mov_b32 flat_scr_lo, -1
+// SI: error: invalid operand for instruction
+// CI-NOT: error
+// VI-NOT: error
+
+s_mov_b32 flat_scr_hi, -1
+// SI: error: invalid operand for instruction
+// CI-NOT: error
+// VI-NOT: error
+
+
+s_mov_b64 flat_scr_lo, -1
+// GCN: error: invalid operand for instruction
+
+s_mov_b64 flat_scr_hi, -1
+// GCN: error: invalid operand for instruction
+
+s_mov_b32 flat_scr, -1
+// GCN: error: invalid operand for instruction
Index: lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
===================================================================
--- lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -331,6 +331,14 @@
 
   unsigned ForcedEncodingSize;
 
+  bool isSI() const {
+    return STI.getFeatureBits()[AMDGPU::FeatureSouthernIslands];
+  }
+
+  bool isCI() const {
+    return STI.getFeatureBits()[AMDGPU::FeatureSeaIslands];
+  }
+
   bool isVI() const {
     return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
   }
@@ -501,12 +509,14 @@
   const AsmToken Tok = Parser.getTok();
   StartLoc = Tok.getLoc();
   EndLoc = Tok.getEndLoc();
+  const MCRegisterInfo *TRI = getContext().getRegisterInfo();
+
   StringRef RegName = Tok.getString();
   RegNo = getRegForName(RegName);
 
   if (RegNo) {
     Parser.Lex();
-    return false;
+    return !subtargetHasRegister(*TRI, RegNo);
   }
 
   // Match vgprs and sgprs
@@ -559,7 +569,6 @@
     }
   }
 
-  const MCRegisterInfo *TRI = getContext().getRegisterInfo();
   int RCID = getRegClass(IsVgpr, RegWidth);
   if (RCID == -1)
     return true;
@@ -962,9 +971,21 @@
 
 bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,
                                            unsigned RegNo) const {
-  if (!isVI())
+  if (isCI())
     return true;
 
+  if (isSI()) {
+    // No flat_scr
+    switch (RegNo) {
+    case AMDGPU::FLAT_SCR:
+    case AMDGPU::FLAT_SCR_LO:
+    case AMDGPU::FLAT_SCR_HI:
+      return false;
+    default:
+      return true;
+    }
+  }
+
   // VI only has 102 SGPRs, so make sure we aren't trying to use the 2 more that
   // SI/CI have.
   for (MCRegAliasIterator R(AMDGPU::SGPR102_SGPR103, &MRI, true);


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