[PATCH] D14082: [ARM] Expand ROTL and ROTR of vector value types

[Charlie Turner via llvm-commits]

chatur01 created this revision.
chatur01 added a reviewer: rengolin.
chatur01 added a subscriber: llvm-commits.
chatur01 set the repository for this revision to rL LLVM.
Herald added subscribers: rengolin, aemerson.

After D13851 landed, we saw backend crashes when compiling the reduced test case included in this patch. The right fix seems to be to allow these vector types for expansion in instruction selection.

Repository:
  rL LLVM

http://reviews.llvm.org/D14082

Files:
  lib/Target/ARM/ARMISelLowering.cpp
  test/CodeGen/ARM/rotate.ll

Index: test/CodeGen/ARM/rotate.ll
===================================================================
--- /dev/null
+++ test/CodeGen/ARM/rotate.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -mtriple=thumbv8--linux-gnueabihf | FileCheck %s
+
+;; This used to cause a backend crash about not being able to
+;; select ROTL. Make sure if generates the basic VSHL/VSHR.
+define <2 x i64> @testcase(<2 x i64>* %in) {
+; CHECK-LABEL: testcase
+; CHECK: vshl.i64
+; CHECK: vshr.u64
+  %1 = load <2 x i64>, <2 x i64>* %in
+  %2 = lshr <2 x i64> %1, <i64 8, i64 8>
+  %3 = shl <2 x i64> %1, <i64 56, i64 56>
+  %4 = or <2 x i64> %2, %3
+  ret <2 x i64> %4
+}
Index: lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- lib/Target/ARM/ARMISelLowering.cpp
+++ lib/Target/ARM/ARMISelLowering.cpp
@@ -718,7 +718,11 @@
   }
 
   // ARM does not have ROTL.
-  setOperationAction(ISD::ROTL,  MVT::i32, Expand);
+  setOperationAction(ISD::ROTL, MVT::i32, Expand);
+  for (MVT VT : MVT::vector_valuetypes()) {
+    setOperationAction(ISD::ROTL, VT, Expand);
+    setOperationAction(ISD::ROTR, VT, Expand);
+  }
   setOperationAction(ISD::CTTZ,  MVT::i32, Custom);
   setOperationAction(ISD::CTPOP, MVT::i32, Expand);
   if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())


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