[llvm] r251296 - [SystemZ] Tie operands in SystemZShorteInst if MI becomes 2-address.

[Jonas Paulsson via llvm-commits]

Author: jonpa
Date: Mon Oct 26 10:03:07 2015
New Revision: 251296

URL: http://llvm.org/viewvc/llvm-project?rev=251296&view=rev
Log:
[SystemZ] Tie operands in SystemZShorteInst if MI becomes 2-address.

Discovered by testing fp-add-02.ll with -verify-machineinstrs.

Test case updated to always run with -verify-machineinstrs.

Modified:
    llvm/trunk/lib/Target/SystemZ/SystemZShortenInst.cpp
    llvm/trunk/test/CodeGen/SystemZ/fp-add-02.ll

Modified: llvm/trunk/lib/Target/SystemZ/SystemZShortenInst.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZShortenInst.cpp?rev=251296&r1=251295&r2=251296&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZShortenInst.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZShortenInst.cpp Mon Oct 26 10:03:07 2015
@@ -59,6 +59,13 @@ FunctionPass *llvm::createSystemZShorten
 SystemZShortenInst::SystemZShortenInst(const SystemZTargetMachine &tm)
   : MachineFunctionPass(ID), TII(nullptr) {}
 
+// Tie operands if MI has become a two-address instruction.
+static void tieOpsIfNeeded(MachineInstr &MI) {
+  if (MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
+      !MI.getOperand(0).isTied())
+    MI.tieOperands(0, 1);
+}
+
 // MI loads one word of a GPR using an IIxF instruction and LLIxL and LLIxH
 // are the halfword immediate loads for the same word.  Try to use one of them
 // instead of IIxF. 
@@ -113,12 +120,14 @@ bool SystemZShortenInst::shortenOn01(Mac
 }
 
 // Change MI's opcode to Opcode if register operands 0, 1 and 2 have a
-// 4-bit encoding and if operands 0 and 1 are tied.
+// 4-bit encoding and if operands 0 and 1 are tied. Also ties op 0
+// with op 1, if MI becomes 2-address.
 bool SystemZShortenInst::shortenOn001(MachineInstr &MI, unsigned Opcode) {
   if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
       MI.getOperand(1).getReg() == MI.getOperand(0).getReg() &&
       SystemZMC::getFirstReg(MI.getOperand(2).getReg()) < 16) {
     MI.setDesc(TII->get(Opcode));
+    tieOpsIfNeeded(MI);
     return true;
   }
   return false;

Modified: llvm/trunk/test/CodeGen/SystemZ/fp-add-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/fp-add-02.ll?rev=251296&r1=251295&r2=251296&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/fp-add-02.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/fp-add-02.ll Mon Oct 26 10:03:07 2015
@@ -2,7 +2,7 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 \
 ; RUN:   | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SCALAR %s
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -verify-machineinstrs | FileCheck %s
 declare double @foo()
 
 ; Check register addition.