[PATCH] D14079: [FPEnv Core 14/14] Introduce F*_W_CHAIN instrs to prevent reordering

[Sergey Dmitrouk via llvm-commits]

sdmitrouk created this revision.
sdmitrouk added reviewers: hfinkel, joker.eph.
sdmitrouk added subscribers: llvm-commits, resistor, scanon.
sdmitrouk set the repository for this revision to rL LLVM.
Herald added subscribers: dsanders, jyknight, arsenm, aemerson, jholewinski.

When floating-point environment is not examined, reordering instructions doesn't
harm, otherwise library call that checks floating-point environment state can be
moved before the actual computation, producing wrong results (not affected by
side-effects of operations).

Repository:
  rL LLVM

http://reviews.llvm.org/D14079

Files:
  include/llvm/CodeGen/ISDOpcodes.h
  include/llvm/CodeGen/SelectionDAG.h
  include/llvm/CodeGen/SelectionDAGNodes.h
  include/llvm/IR/IntrinsicsX86.td
  include/llvm/Target/TargetSelectionDAG.td
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
  lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
  lib/CodeGen/SelectionDAG/LegalizeTypes.h
  lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
  lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
  lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
  lib/CodeGen/SelectionDAG/TargetLowering.cpp
  lib/Target/AArch64/AArch64ISelLowering.cpp
  lib/Target/AArch64/AArch64ISelLowering.h
  lib/Target/AArch64/AArch64InstrInfo.td
  lib/Target/AMDGPU/AMDGPUISelLowering.cpp
  lib/Target/AMDGPU/AMDGPUISelLowering.h
  lib/Target/AMDGPU/AMDGPUInstructions.td
  lib/Target/AMDGPU/CaymanInstructions.td
  lib/Target/AMDGPU/EvergreenInstructions.td
  lib/Target/AMDGPU/R600ISelLowering.cpp
  lib/Target/AMDGPU/R600Instructions.td
  lib/Target/AMDGPU/SIISelLowering.cpp
  lib/Target/AMDGPU/SIInstructions.td
  lib/Target/ARM/ARMISelLowering.cpp
  lib/Target/ARM/ARMInstrNEON.td
  lib/Target/ARM/ARMInstrVFP.td
  lib/Target/Hexagon/HexagonISelLowering.cpp
  lib/Target/Hexagon/HexagonInstrInfoV5.td
  lib/Target/Mips/MipsISelLowering.cpp
  lib/Target/Mips/MipsInstrFPU.td
  lib/Target/NVPTX/NVPTXInstrInfo.td
  lib/Target/PowerPC/PPCISelLowering.cpp
  lib/Target/PowerPC/PPCInstrAltivec.td
  lib/Target/PowerPC/PPCInstrInfo.td
  lib/Target/PowerPC/PPCInstrQPX.td
  lib/Target/PowerPC/PPCInstrVSX.td
  lib/Target/Sparc/SparcISelLowering.cpp
  lib/Target/Sparc/SparcInstrInfo.td
  lib/Target/SystemZ/SystemZISelLowering.cpp
  lib/Target/SystemZ/SystemZInstrFP.td
  lib/Target/SystemZ/SystemZInstrVector.td
  lib/Target/X86/X86FloatingPoint.cpp
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86ISelLowering.h
  lib/Target/X86/X86InstrAVX512.td
  lib/Target/X86/X86InstrFPStack.td
  lib/Target/X86/X86InstrFragmentsSIMD.td
  lib/Target/X86/X86InstrSSE.td
  test/CodeGen/ARM/fpenv-call-order.ll

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