[PATCH] D13708: AArch64: Disable the latency heuristic

[Mailing List "llvm-commits" via llvm-commits]

llvm-commits added a comment.

Thanks for benchmarking. TL;DR: I will change the policy only for Cyclone CPUs.

For the record: I re-checked my results of the llvm-testsuite though I tend to see them less critical than the "big benchmarks" spec*, geekbench* for which the change is neutral for all but two benchmarks which improve by ~10%.

Over the whole llvm-testsuite I have a bunch of ups and downs. Most of the ones in my top 20 are just noisy benchmarks, enc-pc1 regressed only 1% for me which relates to me not seeing any important changes in the assembly, salsa20 shows a 7% regression and it appears to be the first genuine testcase I see where the latency heuristic makes sense because there is indeed a very long loop containing just arithmetic instructions where latency hiding has an effect even on out-of-order CPUs (though it's somewhat unfortunate because the sourcecode was already scheduled in a nice way, llvm performs some impressive load/store optimisations on the benchmark but also reorders the instructions somewhere making the scheduling heuristic necessary. On the other hand I see an improvement of 15% in matmul_f64_4x4.

- Matthias


Repository:
  rL LLVM

http://reviews.llvm.org/D13708