[PATCH] D13922: Restrict tail duplication in the presence of subregisters

[Krzysztof Parzyszek via llvm-commits]

kparzysz added a comment.

IR Dump After Expand ISel Pseudo-instructions
=============================================

  # Machine code for function foo: SSA
  Function Live Ins: %R0 in %vreg3, %D1 in %vreg4
  
  BB#0: derived from LLVM BB %entry
      Live Ins: %R0 %D1
          %vreg4<def> = COPY %D1; DoubleRegs:%vreg4
          %vreg3<def> = COPY %R0; IntRegs:%vreg3
          %vreg5<def> = C2_cmpgti %vreg3, -1; PredRegs:%vreg5 IntRegs:%vreg3
          J2_jumpf %vreg5, <BB#2>, %PC<imp-def,dead>; PredRegs:%vreg5
          J2_jump <BB#1>, %PC<imp-def,dead>
      Successors according to CFG: BB#2(12) BB#1(20)
  
  BB#1: derived from LLVM BB %tail
      Predecessors according to CFG: BB#0 BB#2
          J2_jump <BB#4>, %PC<imp-def,dead>
      Successors according to CFG: BB#4
  
  BB#2: derived from LLVM BB %next
      Predecessors according to CFG: BB#0
          %vreg6<def> = C2_cmpeqi %vreg3, 0; PredRegs:%vreg6 IntRegs:%vreg3
          J2_jumpf %vreg6, <BB#1>, %PC<imp-def,dead>; PredRegs:%vreg6
          J2_jump <BB#3>, %PC<imp-def,dead>
      Successors according to CFG: BB#3(12) BB#1(20)
  
  BB#3: derived from LLVM BB %b1
      Predecessors according to CFG: BB#2
      Successors according to CFG: BB#4
  
  BB#4: derived from LLVM BB %join
      Predecessors according to CFG: BB#1 BB#3
          %vreg2<def> = PHI %vreg4:subreg_loreg, <BB#1>, %vreg4:subreg_hireg, <BB#3>; IntRegs:%vreg2 DoubleRegs:%vreg4
          %R0<def> = COPY %vreg2; IntRegs:%vreg2
          JMPret %R31, %PC<imp-def,dead>, %R0<imp-use>
  
  # End machine code for function foo.
  `

The problem will appear in BB#4:  the phi node mixed registers from IntRegs and DoubleRegs.  On Hexagon, a register from DoubleRegs is a pair of IntRegs, and subreg_loreg/subreg_hireg are the low/high register from that pair.  In that sense, DoubleReg with a subregister is "equivalent" to IntReg, but without any subregisters, it is not copyable into an IntReg.

  # *** IR Dump After Tail Duplication ***:
  # Machine code for function foo: SSA
  Function Live Ins: %R0 in %vreg3, %D1 in %vreg4
  
  BB#0: derived from LLVM BB %entry
      Live Ins: %R0 %D1
          %vreg4<def> = COPY %D1; DoubleRegs:%vreg4
          %vreg3<def> = COPY %R0; IntRegs:%vreg3
          %vreg5<def> = C2_cmpgti %vreg3, -1; PredRegs:%vreg5 IntRegs:%vreg3
          J2_jumpf %vreg5, <BB#2>, %PC<imp-def>; PredRegs:%vreg5
          J2_jump <BB#4>, %PC<imp-def>
      Successors according to CFG: BB#2(12) BB#4(20)
  
  BB#2: derived from LLVM BB %next
      Predecessors according to CFG: BB#0
          %vreg6<def> = C2_cmpeqi %vreg3, 0; PredRegs:%vreg6 IntRegs:%vreg3
          J2_jumpf %vreg6, <BB#4>, %PC<imp-def>; PredRegs:%vreg6
      Successors according to CFG: BB#3(12) BB#4(20)
  
  BB#3: derived from LLVM BB %b1
      Predecessors according to CFG: BB#2
      Successors according to CFG: BB#4
  
  BB#4: derived from LLVM BB %join
      Predecessors according to CFG: BB#3 BB#0 BB#2
          %vreg2<def> = PHI %vreg4:subreg_loreg, <BB#0>, %vreg4:subreg_hireg, <BB#3>, %vreg4, <BB#2>; IntRegs:%vreg2 DoubleRegs:%vreg4
          %R0<def> = COPY %vreg2; IntRegs:%vreg2
          JMPret %R31, %PC<imp-def,dead>, %R0<imp-use>
  
  # End machine code for function foo.


Repository:
  rL LLVM

http://reviews.llvm.org/D13922