[PATCH] D13649: [mips] Clang ll/sc illegal instruction on mips64r2 with -O0

[Vasileios Kalintiris via llvm-commits]

vkalintiris added inline comments.

================
Comment at: lib/Target/Mips/MipsISelLowering.cpp:1477-1502
@@ -1475,28 +1476,28 @@
   int64_t MaskImm = (Size == 1) ? 255 : 65535;
   BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
     .addReg(Mips::ZERO).addImm(-4);
   BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
     .addReg(Ptr).addReg(MaskLSB2);
   BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
   if (Subtarget.isLittle()) {
     BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
   } else {
     unsigned Off = RegInfo.createVirtualRegister(RC);
     BuildMI(BB, DL, TII->get(Mips::XORi), Off)
       .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
     BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
   }
   BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
     .addReg(Mips::ZERO).addImm(MaskImm);
   BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
     .addReg(MaskUpper).addReg(ShiftAmt);
   BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
   BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
     .addReg(CmpVal).addImm(MaskImm);
   BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
     .addReg(MaskedCmpVal).addReg(ShiftAmt);
   BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
     .addReg(NewVal).addImm(MaskImm);
   BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
     .addReg(MaskedNewVal).addReg(ShiftAmt);
 
----------------
We should specify the correct instructions, based on the register class, to every `TII->get()` in this function. For example, you could use something like that: `unsigned NOR = Subtarget.isGP64bit() ? Mips::NOR64 : Mips::NOR;` for every opcode we want to use.

================
Comment at: test/CodeGen/Mips/at.ll:1-19
@@ +1,18 @@
+; RUN: llc  -O0 -march=mips64el -mcpu=mips64r2 < %s -filetype=asm -o - \
+; RUN:   | FileCheck %s -implicit-check-not=lw
+
+ at _ZZ14InitializeOncevE5array = global [1 x i32*] zeroinitializer, align 8
+ at _ZGVZ14InitializeOncevE5array = global i64 0, align 8
+
+define void @_Z14InitializeOncev()
+#0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+entry:
+  %exn.slot = alloca i8*
+  %ehselector.slot = alloca i32
+  %0 = load atomic i8,
+     i8* bitcast (i64* @_ZGVZ14InitializeOncevE5array to i8*) acquire, align 8
+  ret void
+}
+
+
+declare i32 @__gxx_personality_v0(...)
\ No newline at end of file

----------------
The test seems fine but could use a more meaningful filename, eg. `test-atomic-cmp-swap.ll` or something similar?


http://reviews.llvm.org/D13649