[llvm] r250497 - [X86] Add fxsr feature flag for fxsave/fxrestore instructions.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 15 23:03:10 PDT 2015
Author: ctopper
Date: Fri Oct 16 01:03:09 2015
New Revision: 250497
URL: http://llvm.org/viewvc/llvm-project?rev=250497&view=rev
Log:
[X86] Add fxsr feature flag for fxsave/fxrestore instructions.
Modified:
llvm/trunk/lib/Target/X86/X86.td
llvm/trunk/lib/Target/X86/X86InstrFPStack.td
llvm/trunk/lib/Target/X86/X86InstrInfo.td
llvm/trunk/lib/Target/X86/X86Subtarget.cpp
llvm/trunk/lib/Target/X86/X86Subtarget.h
llvm/trunk/test/CodeGen/X86/system-intrinsics-64.ll
llvm/trunk/test/CodeGen/X86/system-intrinsics.ll
Modified: llvm/trunk/lib/Target/X86/X86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=250497&r1=250496&r2=250497&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86.td (original)
+++ llvm/trunk/lib/Target/X86/X86.td Fri Oct 16 01:03:09 2015
@@ -37,6 +37,9 @@ def FeatureCMOV : SubtargetFeature<"c
def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
"Support POPCNT instruction">;
+def FeatureFXSR : SubtargetFeature<"fxsr", "HasFXSR", "true",
+ "Support fxsave/fxrestore instructions">;
+
def FeatureXSAVE : SubtargetFeature<"xsave", "HasXSAVE", "true",
"Support xsave instructions">;
@@ -233,28 +236,33 @@ def : Proc<"pentium", [FeatureSl
def : Proc<"pentium-mmx", [FeatureSlowUAMem16, FeatureMMX]>;
def : Proc<"i686", [FeatureSlowUAMem16]>;
def : Proc<"pentiumpro", [FeatureSlowUAMem16, FeatureCMOV]>;
-def : Proc<"pentium2", [FeatureSlowUAMem16, FeatureMMX, FeatureCMOV]>;
-def : Proc<"pentium3", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1]>;
+def : Proc<"pentium2", [FeatureSlowUAMem16, FeatureMMX, FeatureCMOV,
+ FeatureFXSR]>;
+def : Proc<"pentium3", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1,
+ FeatureFXSR]>;
def : Proc<"pentium3m", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1,
- FeatureSlowBTMem]>;
+ FeatureFXSR, FeatureSlowBTMem]>;
def : Proc<"pentium-m", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
- FeatureSlowBTMem]>;
-def : Proc<"pentium4", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2]>;
+ FeatureFXSR, FeatureSlowBTMem]>;
+def : Proc<"pentium4", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
+ FeatureFXSR]>;
def : Proc<"pentium4m", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
- FeatureSlowBTMem]>;
+ FeatureFXSR, FeatureSlowBTMem]>;
// Intel Core Duo.
-def : ProcessorModel<
- "yonah", SandyBridgeModel,
- [ FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureSlowBTMem ]>;
+def : ProcessorModel<"yonah", SandyBridgeModel,
+ [FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureFXSR,
+ FeatureSlowBTMem]>;
// NetBurst.
def : Proc<"prescott",
- [ FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureSlowBTMem ]>;
+ [FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureFXSR,
+ FeatureSlowBTMem]>;
def : Proc<"nocona", [
FeatureSlowUAMem16,
FeatureMMX,
FeatureSSE3,
+ FeatureFXSR,
FeatureCMPXCHG16B,
FeatureSlowBTMem
]>;
@@ -264,6 +272,7 @@ def : ProcessorModel<"core2", SandyBridg
FeatureSlowUAMem16,
FeatureMMX,
FeatureSSSE3,
+ FeatureFXSR,
FeatureCMPXCHG16B,
FeatureSlowBTMem
]>;
@@ -271,6 +280,7 @@ def : ProcessorModel<"penryn", SandyBrid
FeatureSlowUAMem16,
FeatureMMX,
FeatureSSE41,
+ FeatureFXSR,
FeatureCMPXCHG16B,
FeatureSlowBTMem
]>;
@@ -281,6 +291,7 @@ class BonnellProc<string Name> : Process
FeatureSlowUAMem16,
FeatureMMX,
FeatureSSSE3,
+ FeatureFXSR,
FeatureCMPXCHG16B,
FeatureMOVBE,
FeatureSlowBTMem,
@@ -298,6 +309,7 @@ class SilvermontProc<string Name> : Proc
ProcIntelSLM,
FeatureMMX,
FeatureSSE42,
+ FeatureFXSR,
FeatureCMPXCHG16B,
FeatureMOVBE,
FeaturePOPCNT,
@@ -317,6 +329,7 @@ def : SilvermontProc<"slm">; // Legacy a
class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
FeatureMMX,
FeatureSSE42,
+ FeatureFXSR,
FeatureCMPXCHG16B,
FeatureSlowBTMem,
FeaturePOPCNT
@@ -329,6 +342,7 @@ def : NehalemProc<"corei7">;
class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
FeatureMMX,
FeatureSSE42,
+ FeatureFXSR,
FeatureCMPXCHG16B,
FeatureSlowBTMem,
FeaturePOPCNT,
@@ -342,6 +356,7 @@ def : WestmereProc<"westmere">;
class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
FeatureMMX,
FeatureAVX,
+ FeatureFXSR,
FeatureCMPXCHG16B,
FeatureSlowBTMem,
FeatureSlowUAMem32,
@@ -357,6 +372,7 @@ def : SandyBridgeProc<"corei7-avx">; //
class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
FeatureMMX,
FeatureAVX,
+ FeatureFXSR,
FeatureCMPXCHG16B,
FeatureSlowBTMem,
FeatureSlowUAMem32,
@@ -375,6 +391,7 @@ def : IvyBridgeProc<"core-avx-i">; // Le
class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [
FeatureMMX,
FeatureAVX2,
+ FeatureFXSR,
FeatureCMPXCHG16B,
FeatureSlowBTMem,
FeaturePOPCNT,
@@ -400,6 +417,7 @@ def : HaswellProc<"core-avx2">; // Legac
class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
FeatureMMX,
FeatureAVX2,
+ FeatureFXSR,
FeatureCMPXCHG16B,
FeatureSlowBTMem,
FeaturePOPCNT,
@@ -427,6 +445,7 @@ def : BroadwellProc<"broadwell">;
class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel, [
FeatureMMX,
FeatureAVX512,
+ FeatureFXSR,
FeatureERI,
FeatureCDI,
FeaturePFI,
@@ -455,6 +474,7 @@ def : KnightsLandingProc<"knl">;
class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel, [
FeatureMMX,
FeatureAVX512,
+ FeatureFXSR,
FeatureCDI,
FeatureDQI,
FeatureBWI,
@@ -497,46 +517,45 @@ def : Proc<"athlon", [FeatureSl
def : Proc<"athlon-tbird", [FeatureSlowUAMem16, Feature3DNowA,
FeatureSlowBTMem, FeatureSlowSHLD]>;
def : Proc<"athlon-4", [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
- FeatureSlowBTMem, FeatureSlowSHLD]>;
+ FeatureFXSR, FeatureSlowBTMem, FeatureSlowSHLD]>;
def : Proc<"athlon-xp", [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
- FeatureSlowBTMem, FeatureSlowSHLD]>;
+ FeatureFXSR, FeatureSlowBTMem, FeatureSlowSHLD]>;
def : Proc<"athlon-mp", [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
- FeatureSlowBTMem, FeatureSlowSHLD]>;
+ FeatureFXSR, FeatureSlowBTMem, FeatureSlowSHLD]>;
def : Proc<"k8", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
- Feature64Bit, FeatureSlowBTMem,
+ FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
FeatureSlowSHLD]>;
def : Proc<"opteron", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
- Feature64Bit, FeatureSlowBTMem,
+ FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
FeatureSlowSHLD]>;
def : Proc<"athlon64", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
- Feature64Bit, FeatureSlowBTMem,
+ FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
FeatureSlowSHLD]>;
def : Proc<"athlon-fx", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
- Feature64Bit, FeatureSlowBTMem,
+ FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
FeatureSlowSHLD]>;
def : Proc<"k8-sse3", [FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA,
- FeatureCMPXCHG16B, FeatureSlowBTMem,
+ FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowBTMem,
FeatureSlowSHLD]>;
def : Proc<"opteron-sse3", [FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA,
- FeatureCMPXCHG16B, FeatureSlowBTMem,
+ FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowBTMem,
FeatureSlowSHLD]>;
def : Proc<"athlon64-sse3", [FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA,
- FeatureCMPXCHG16B, FeatureSlowBTMem,
- FeatureSlowSHLD]>;
-def : Proc<"amdfam10", [FeatureSSE4A,
- Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
- FeaturePOPCNT, FeatureSlowBTMem,
- FeatureSlowSHLD]>;
-def : Proc<"barcelona", [FeatureSSE4A,
- Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
- FeaturePOPCNT, FeatureSlowBTMem,
+ FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowBTMem,
FeatureSlowSHLD]>;
+def : Proc<"amdfam10", [FeatureSSE4A, Feature3DNowA, FeatureFXSR,
+ FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT,
+ FeatureSlowBTMem, FeatureSlowSHLD]>;
+def : Proc<"barcelona", [FeatureSSE4A, Feature3DNowA, FeatureFXSR,
+ FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT,
+ FeatureSlowBTMem, FeatureSlowSHLD]>;
// Bobcat
def : Proc<"btver1", [
FeatureMMX,
FeatureSSSE3,
FeatureSSE4A,
+ FeatureFXSR,
FeatureCMPXCHG16B,
FeaturePRFCHW,
FeatureLZCNT,
@@ -549,6 +568,7 @@ def : Proc<"btver1", [
def : ProcessorModel<"btver2", BtVer2Model, [
FeatureMMX,
FeatureAVX,
+ FeatureFXSR,
FeatureSSE4A,
FeatureCMPXCHG16B,
FeaturePRFCHW,
@@ -574,6 +594,7 @@ def : Proc<"bdver1", [
FeaturePCLMUL,
FeatureMMX,
FeatureAVX,
+ FeatureFXSR,
FeatureSSE4A,
FeatureLZCNT,
FeaturePOPCNT,
@@ -590,6 +611,7 @@ def : Proc<"bdver2", [
FeaturePCLMUL,
FeatureMMX,
FeatureAVX,
+ FeatureFXSR,
FeatureSSE4A,
FeatureF16C,
FeatureLZCNT,
@@ -611,6 +633,7 @@ def : Proc<"bdver3", [
FeaturePCLMUL,
FeatureMMX,
FeatureAVX,
+ FeatureFXSR,
FeatureSSE4A,
FeatureF16C,
FeatureLZCNT,
@@ -628,6 +651,7 @@ def : Proc<"bdver3", [
def : Proc<"bdver4", [
FeatureMMX,
FeatureAVX2,
+ FeatureFXSR,
FeatureXOP,
FeatureFMA4,
FeatureCMPXCHG16B,
@@ -651,7 +675,7 @@ def : Proc<"geode", [FeatureSl
def : Proc<"winchip-c6", [FeatureSlowUAMem16, FeatureMMX]>;
def : Proc<"winchip2", [FeatureSlowUAMem16, Feature3DNow]>;
def : Proc<"c3", [FeatureSlowUAMem16, Feature3DNow]>;
-def : Proc<"c3-2", [ FeatureSlowUAMem16, FeatureMMX, FeatureSSE1 ]>;
+def : Proc<"c3-2", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1, FeatureFXSR]>;
// We also provide a generic 64-bit specific x86 processor model which tries to
// be good for modern chips without enabling instruction set encodings past the
@@ -663,9 +687,9 @@ def : Proc<"c3-2", [ FeatureSlowUAMem16,
// covers a huge swath of x86 processors. If there are specific scheduling
// knobs which need to be tuned differently for AMD chips, we might consider
// forming a common base for them.
-def : ProcessorModel<
- "x86-64", SandyBridgeModel,
- [ FeatureMMX, FeatureSSE2, Feature64Bit, FeatureSlowBTMem ]>;
+def : ProcessorModel<"x86-64", SandyBridgeModel,
+ [FeatureMMX, FeatureSSE2, FeatureFXSR, Feature64Bit,
+ FeatureSlowBTMem ]>;
//===----------------------------------------------------------------------===//
// Register File Description
Modified: llvm/trunk/lib/Target/X86/X86InstrFPStack.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFPStack.td?rev=250497&r1=250496&r2=250497&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFPStack.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFPStack.td Fri Oct 16 01:03:09 2015
@@ -633,16 +633,18 @@ def FRNDINT : I<0xD9, MRM_FC, (outs), (i
def FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", [], IIC_FSCALE>;
def FCOMPP : I<0xDE, MRM_D9, (outs), (ins), "fcompp", [], IIC_FCOMPP>;
-def FXSAVE : I<0xAE, MRM0m, (outs), (ins opaque512mem:$dst),
- "fxsave\t$dst", [(int_x86_fxsave addr:$dst)], IIC_FXSAVE>, TB;
-def FXSAVE64 : RI<0xAE, MRM0m, (outs), (ins opaque512mem:$dst),
- "fxsave64\t$dst", [(int_x86_fxsave64 addr:$dst)],
- IIC_FXSAVE>, TB, Requires<[In64BitMode]>;
-def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaque512mem:$src),
- "fxrstor\t$src", [(int_x86_fxrstor addr:$src)], IIC_FXRSTOR>, TB;
-def FXRSTOR64 : RI<0xAE, MRM1m, (outs), (ins opaque512mem:$src),
- "fxrstor64\t$src", [(int_x86_fxrstor64 addr:$src)],
- IIC_FXRSTOR>, TB, Requires<[In64BitMode]>;
+let Predicates = [HasFXSR] in {
+ def FXSAVE : I<0xAE, MRM0m, (outs), (ins opaque512mem:$dst),
+ "fxsave\t$dst", [(int_x86_fxsave addr:$dst)], IIC_FXSAVE>, TB;
+ def FXSAVE64 : RI<0xAE, MRM0m, (outs), (ins opaque512mem:$dst),
+ "fxsave64\t$dst", [(int_x86_fxsave64 addr:$dst)],
+ IIC_FXSAVE>, TB, Requires<[In64BitMode]>;
+ def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaque512mem:$src),
+ "fxrstor\t$src", [(int_x86_fxrstor addr:$src)], IIC_FXRSTOR>, TB;
+ def FXRSTOR64 : RI<0xAE, MRM1m, (outs), (ins opaque512mem:$src),
+ "fxrstor64\t$src", [(int_x86_fxrstor64 addr:$src)],
+ IIC_FXRSTOR>, TB, Requires<[In64BitMode]>;
+} // Predicates = [FeatureFXSR]
} // SchedRW
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=250497&r1=250496&r2=250497&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Fri Oct 16 01:03:09 2015
@@ -773,6 +773,7 @@ def NoVLX_Or_NoBWI : Predicate<"!Subtarg
def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
def HasAES : Predicate<"Subtarget->hasAES()">;
+def HasFXSR : Predicate<"Subtarget->hasFXSR()">;
def HasXSAVE : Predicate<"Subtarget->hasXSAVE()">;
def HasXSAVEOPT : Predicate<"Subtarget->hasXSAVEOPT()">;
def HasXSAVEC : Predicate<"Subtarget->hasXSAVEC()">;
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=250497&r1=250496&r2=250497&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Fri Oct 16 01:03:09 2015
@@ -236,6 +236,7 @@ void X86Subtarget::initializeEnvironment
HasPOPCNT = false;
HasSSE4A = false;
HasAES = false;
+ HasFXSR = false;
HasXSAVE = false;
HasXSAVEOPT = false;
HasXSAVEC = false;
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=250497&r1=250496&r2=250497&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.h Fri Oct 16 01:03:09 2015
@@ -89,6 +89,9 @@ protected:
/// Target has AES instructions
bool HasAES;
+ /// Target has FXSAVE/FXRESTOR instructions
+ bool HasFXSR;
+
/// Target has XSAVE instructions
bool HasXSAVE;
/// Target has XSAVEOPT instructions
@@ -348,6 +351,7 @@ public:
bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
bool hasPOPCNT() const { return HasPOPCNT; }
bool hasAES() const { return HasAES; }
+ bool hasFXSR() const { return HasFXSR; }
bool hasXSAVE() const { return HasXSAVE; }
bool hasXSAVEOPT() const { return HasXSAVEOPT; }
bool hasXSAVEC() const { return HasXSAVEC; }
Modified: llvm/trunk/test/CodeGen/X86/system-intrinsics-64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/system-intrinsics-64.ll?rev=250497&r1=250496&r2=250497&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/system-intrinsics-64.ll (original)
+++ llvm/trunk/test/CodeGen/X86/system-intrinsics-64.ll Fri Oct 16 01:03:09 2015
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+fxsr | FileCheck %s
define void @test_fxsave(i8* %ptr) {
; CHECK-LABEL: test_fxsave
Modified: llvm/trunk/test/CodeGen/X86/system-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/system-intrinsics.ll?rev=250497&r1=250496&r2=250497&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/system-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/X86/system-intrinsics.ll Fri Oct 16 01:03:09 2015
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+fxsr | FileCheck %s
define void @test_fxsave(i8* %ptr) {
; CHECK-LABEL: test_fxsave
More information about the llvm-commits
mailing list