[PATCH] D13771: [AArch64]Add support for converting halfword loads into a 32-bit word load

[Chad Rosier via llvm-commits]

mcrosier added inline comments.

================
Comment at: lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp:1108
@@ -1015,1 +1107,3 @@
   //        ldr x0, [x2], #4
+  // 3) Find halfword loads that can be merged into a single 32-bit word load
+  //    with bitfield extract instructions.
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I would also make this the first listed optimization.  That way the documentation is consistent with the order in which the optimization occur.

1. combining of halfword/small types opt
2. load/store paring opt
3. pre- and post-index opt


http://reviews.llvm.org/D13771