[PATCH] D13771: [AArch64]Add support for converting halfword loads into a 32-bit word load

[Chad Rosier via llvm-commits]

mcrosier added a comment.

Hi Jun,
Just a few general comments:

1. You might want to consider pulling this optimization into a separate loop before the loop the does the load and store pairing.  I could see a case where you promote the ldrh+ldrh into a ldr and then that ldr gets paired with another ldr into a ldp.

ldrh w1, [x0]
ldrh w2, [x0, #2]
ldrh w3, [x0, #4]
ldrh w4, [x0, #8]

becomes something like:

ldp w1, w3 [x0]
ubfx w2, w1, #16, #16
ubfx w1, w1, #0, #16
ubfx w4, w3, #16, #16
ubfx w3,  w3, #0, #16

2. For the suggestion in #1 to work you would need to append the MMOs to the new ldr instruction.  Otherwise, the hasOrderedMemoryRef() check will fail.

3. Would is make sense to use an 'and w0, w0, 0xff' to zero the upper bits of the load?  In other words, I'm wondering if a 'ubfx' is more expensive than an 'and' operation?

  Chad


================
Comment at: lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp:168
@@ +167,3 @@
+  case AArch64::LDRHHui:
+    return true;
+  case AArch64::LDURHHi:
----------------
Just delete and fall through.


http://reviews.llvm.org/D13771