[PATCH] D13771: [AArch64]Add support for converting halfword loads into a 32-bit word load

Jun Bum Lim via llvm-commits llvm-commits at lists.llvm.org
Thu Oct 15 07:43:05 PDT 2015


junbuml created this revision.
junbuml added reviewers: mcrosier, mzolotukhin.
junbuml added a subscriber: llvm-commits.
Herald added subscribers: rengolin, aemerson.

Convert two halfword loads into a single 32-bit word load with bitfield extract
instructions. For example :
  ldrh w0, [x2]
  ldrh w1, [x2, #2]
becomes
  ldr w0, [x2]
  ubfx w1, w0, #16, #16
  ubfx w0, w0, #0, #16

http://reviews.llvm.org/D13771

Files:
  lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
  test/CodeGen/AArch64/arm64-ldp.ll

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