[PATCH] D13649: [mips] Clang ll/sc illegal instruction on mips64r2 with -O0

[Jelena Losic via llvm-commits]

Jelena.Losic updated this revision to Diff 37470.
Jelena.Losic added a comment.

I put code changes according to Vasileios suggestions.


http://reviews.llvm.org/D13649

Files:
  lib/Target/Mips/MipsISelLowering.cpp
  test/CodeGen/Mips/at.ll

Index: test/CodeGen/Mips/at.ll
===================================================================
--- test/CodeGen/Mips/at.ll
+++ test/CodeGen/Mips/at.ll
@@ -0,0 +1,18 @@
+; RUN: llc   -march=mips64el -mcpu=mips64r2 < %s -filetype=obj -o - \
+; RUN:   | FileCheck %s -implicit-check-not=lw
+
+ at _ZZ14InitializeOncevE5array = global [1 x i32*] zeroinitializer, align 8
+ at _ZGVZ14InitializeOncevE5array = global i64 0, align 8
+
+define void @_Z14InitializeOncev()
+#0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+entry:
+  %exn.slot = alloca i8*
+  %ehselector.slot = alloca i32
+  %0 = load atomic i8,
+     i8* bitcast (i64* @_ZGVZ14InitializeOncevE5array to i8*) acquire, align 8
+  ret void
+}
+
+
+declare i32 @__gxx_personality_v0(...)
\ No newline at end of file
Index: lib/Target/Mips/MipsISelLowering.cpp
===================================================================
--- lib/Target/Mips/MipsISelLowering.cpp
+++ lib/Target/Mips/MipsISelLowering.cpp
@@ -1407,7 +1407,8 @@
 
   MachineFunction *MF = BB->getParent();
   MachineRegisterInfo &RegInfo = MF->getRegInfo();
-  const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
+  const TargetRegisterClass *RC =
+    getRegClassFor(Subtarget.isABI_N64() ? MVT::i64 : MVT::i32);
   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
   DebugLoc DL = MI->getDebugLoc();
 
@@ -1505,7 +1506,14 @@
   //    and     maskedoldval0,oldval,mask
   //    bne     maskedoldval0,shiftedcmpval,sinkMBB
   BB = loop1MBB;
-  unsigned LL = isMicroMips ? Mips::LL_MM : Mips::LL;
+  unsigned LL, SC;
+  if (isMicroMips) {
+       LL = Mips::LL_MM;
+       SC = Mips::SC_MM;
+     } else {
+       LL = Subtarget.hasMips32r6() ? Mips::LL_R6 : Mips::LL;
+       SC = Subtarget.hasMips32r6() ? Mips::SC_R6 : Mips::SC;
+     }
   BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
   BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
     .addReg(OldVal).addReg(Mask);
@@ -1522,7 +1530,6 @@
     .addReg(OldVal).addReg(Mask2);
   BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
     .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
-  unsigned SC = isMicroMips ? Mips::SC_MM : Mips::SC;
   BuildMI(BB, DL, TII->get(SC), Success)
       .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
   BuildMI(BB, DL, TII->get(Mips::BEQ))


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