[llvm] r250381 - [mips][microMIPS] Implement BREAK16, LI16, MOVE16, SDBBP16, SUBU16 and XOR16 instructions
Hrvoje Varga via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 15 01:39:08 PDT 2015
Author: hvarga
Date: Thu Oct 15 03:39:07 2015
New Revision: 250381
URL: http://llvm.org/viewvc/llvm-project?rev=250381&view=rev
Log:
[mips][microMIPS] Implement BREAK16, LI16, MOVE16, SDBBP16, SUBU16 and XOR16 instructions
Differential Revision: http://reviews.llvm.org/D11292#inline-103143
Modified:
llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td
llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt
llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt
llvm/trunk/test/MC/Mips/micromips32r6/valid.s
llvm/trunk/test/MC/Mips/micromips64r6/valid.s
Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td?rev=250381&r1=250380&r2=250381&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td Thu Oct 15 03:39:07 2015
@@ -632,7 +632,7 @@ class POOL16C_NOT16_FM_MMR6 : MicroMipsR
let Inst{3-0} = 0b0000;
}
-class POOL16C_OR16_FM_MMR6 : MicroMipsR6Inst16 {
+class POOL16C_OR16_XOR16_FM_MMR6<bits<4> op> {
bits<3> rt;
bits<3> rs;
@@ -641,7 +641,30 @@ class POOL16C_OR16_FM_MMR6 : MicroMipsR6
let Inst{15-10} = 0b010001;
let Inst{9-7} = rt;
let Inst{6-4} = rs;
- let Inst{3-0} = 0b1001;
+ let Inst{3-0} = op;
+}
+
+class POOL16C_BREAKPOINT_FM_MMR6<bits<6> op> {
+ bits<4> code_;
+ bits<16> Inst;
+
+ let Inst{15-10} = 0b010001;
+ let Inst{9-6} = code_;
+ let Inst{5-0} = op;
+}
+
+class POOL16A_SUBU16_FM_MMR6 {
+ bits<3> rs;
+ bits<3> rt;
+ bits<3> rd;
+
+ bits<16> Inst;
+
+ let Inst{15-10} = 0b000001;
+ let Inst{9-7} = rs;
+ let Inst{6-4} = rt;
+ let Inst{3-1} = rd;
+ let Inst{0} = 0b1;
}
class POOL32A_WRPGPR_WSBH_FM_MMR6<bits<10> funct> : MipsR6Inst {
Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td?rev=250381&r1=250380&r2=250381&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td Thu Oct 15 03:39:07 2015
@@ -112,9 +112,15 @@ class ADDU16_MMR6_ENC : POOL16A_ADDU16_F
class AND16_MMR6_ENC : POOL16C_AND16_FM_MMR6;
class ANDI16_MMR6_ENC : ANDI_FM_MM16<0b001011>, MicroMipsR6Inst16;
class NOT16_MMR6_ENC : POOL16C_NOT16_FM_MMR6;
-class OR16_MMR6_ENC : POOL16C_OR16_FM_MMR6;
+class OR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1001>;
class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>, MicroMipsR6Inst16;
class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>, MicroMipsR6Inst16;
+class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>;
+class LI16_MMR6_ENC : LI_FM_MM16;
+class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>;
+class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>;
+class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6;
+class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>;
class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
RegisterOperand GPROpnd>
@@ -692,18 +698,30 @@ class LOAD_WORD_EVA_MMR6_DESC_BASE<strin
class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd>;
class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd>;
class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
- MMR6Arch<"addu16">;
+ MMR6Arch<"addu16">;
class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
- MMR6Arch<"and16">;
+ MMR6Arch<"and16">;
class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>,
- MMR6Arch<"andi16">;
+ MMR6Arch<"andi16">;
class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16">;
class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
- MMR6Arch<"or16">;
+ MMR6Arch<"or16">;
class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
- MMR6Arch<"sll16">;
+ MMR6Arch<"sll16">;
class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
- MMR6Arch<"srl16">;
+ MMR6Arch<"srl16">;
+class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16">, MMR6Arch<"srl16">,
+ MicroMipsR6Inst16;
+class LI16_MMR6_DESC : LoadImmMM16<"li16", li_simm7, GPRMM16Opnd>,
+ MMR6Arch<"srl16">, MicroMipsR6Inst16, IsAsCheapAsAMove;
+class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"srl16">,
+ MicroMipsR6Inst16;
+class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16">, MMR6Arch<"sdbbp16">,
+ MicroMipsR6Inst16;
+class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
+ MMR6Arch<"sdbbp16">, MicroMipsR6Inst16;
+class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
+ MMR6Arch<"sdbbp16">, MicroMipsR6Inst16;
class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst {
dag OutOperandList = (outs GPR32Opnd:$rt);
@@ -944,6 +962,18 @@ def SLL16_MMR6 : StdMMR6Rel, SLL16_MMR6_
ISA_MICROMIPS32R6;
def SRL16_MMR6 : StdMMR6Rel, SRL16_MMR6_DESC, SRL16_MMR6_ENC,
ISA_MICROMIPS32R6;
+def BREAK16_MMR6 : StdMMR6Rel, BREAK16_MMR6_DESC, BREAK16_MMR6_ENC,
+ ISA_MICROMIPS32R6;
+def LI16_MMR6 : StdMMR6Rel, LI16_MMR6_DESC, LI16_MMR6_ENC,
+ ISA_MICROMIPS32R6;
+def MOVE16_MMR6 : StdMMR6Rel, MOVE16_MMR6_DESC, MOVE16_MMR6_ENC,
+ ISA_MICROMIPS32R6;
+def SDBBP16_MMR6 : StdMMR6Rel, SDBBP16_MMR6_DESC, SDBBP16_MMR6_ENC,
+ ISA_MICROMIPS32R6;
+def SUBU16_MMR6 : StdMMR6Rel, SUBU16_MMR6_DESC, SUBU16_MMR6_ENC,
+ ISA_MICROMIPS32R6;
+def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC,
+ ISA_MICROMIPS32R6;
}
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=250381&r1=250380&r2=250381&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Thu Oct 15 03:39:07 2015
@@ -604,9 +604,9 @@ def SRL16_MM : ShiftIMM16<"srl16", uimm3
SHIFT_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6_64R6;
def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
- ARITH_FM_MM16<1>;
+ ARITH_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6_64R6;
def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
- LOGIC_FM_MM16<0x1>;
+ LOGIC_FM_MM16<0x1>, ISA_MICROMIPS_NOT_32R6_64R6;
def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU,
mem_mm_4>, LOAD_STORE_FM_MM16<0x02>;
def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU,
@@ -647,8 +647,10 @@ def BEQZ16_MM : CBranchZeroMM<"beqz16",
def BNEZ16_MM : CBranchZeroMM<"bnez16", brtarget7_mm, GPRMM16Opnd>,
BEQNEZ_FM_MM16<0x2b>;
def B16_MM : UncondBranchMM16<"b16">, B16_FM;
-def BREAK16_MM : BrkSdbbp16MM<"break16">, BRKSDBBP16_FM_MM<0x28>;
-def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16">, BRKSDBBP16_FM_MM<0x2C>;
+def BREAK16_MM : BrkSdbbp16MM<"break16">, BRKSDBBP16_FM_MM<0x28>,
+ ISA_MICROMIPS_NOT_32R6_64R6;
+def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16">, BRKSDBBP16_FM_MM<0x2C>,
+ ISA_MICROMIPS_NOT_32R6_64R6;
class WaitMM<string opstr> :
InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt?rev=250381&r1=250380&r2=250381&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt Thu Oct 15 03:39:07 2015
@@ -195,3 +195,22 @@
0x03 0xb0 0xfa 0x3c # CHECK: tltu $16, $sp, 15
0x02 0x26 0x0c 0x3c # CHECK: tne $6, $17
0x01 0x07 0xfc 0x3c # CHECK: tne $7, $8, 15
+0x65 0x88 # CHECK: lw $3, 32($gp)
+0x48 0x66 # CHECK: lw $3, 24($sp)
+0x6a 0x12 # CHECK: lw16 $4, 8($17)
+0x29 0x82 # CHECK: lhu16 $3, 4($16)
+0x09 0x94 # CHECK: lbu16 $3, 4($17)
+0x09 0x9f # CHECK: lbu16 $3, -1($17)
+0x04 0xcc # CHECK: addu16 $6, $17, $4
+0x44 0x21 # CHECK: and16 $16, $2
+0x2e 0x56 # CHECK: andi16 $4, $5, 8
+0x46 0x70 # CHECK: not16 $4, $7
+0x45 0xf9 # CHECK: or16 $3, $7
+0x25 0xe0 # CHECK: sll16 $3, $6, 8
+0x25 0xe1 # CHECK: srl16 $3, $6, 8
+0x46 0x1B # CHECK: break16 8
+0xed 0xff # CHECK: li16 $3, -1
+0x0c 0x65 # CHECK: move16 $3, $5
+0x46 0x3b # CHECK: sdbbp16 8
+0x04 0x3b # CHECK: subu16 $5, $16, $3
+0x44 0xd8 # CHECK: xor16 $17, $5
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt?rev=250381&r1=250380&r2=250381&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt Thu Oct 15 03:39:07 2015
@@ -131,3 +131,15 @@
0x60 0x25 0xa6 0x08 # CHECK: cachee 1, 8($5)
0x00 0x64 0xf1 0x7c # CHECK: wrpgpr $3, $4
0x00 0x64 0x7b 0x3c # CHECK: wsbh $3, $4
+0x65 0x88 # CHECK: lw $3, 32($gp)
+0x48 0x66 # CHECK: lw $3, 24($sp)
+0x6a 0x12 # CHECK: lw16 $4, 8($17)
+0x29 0x82 # CHECK: lhu16 $3, 4($16)
+0x09 0x94 # CHECK: lbu16 $3, 4($17)
+0x09 0x9f # CHECK: lbu16 $3, -1($17)
+0x46 0x1B # CHECK: break16 8
+0xed 0xff # CHECK: li16 $3, -1
+0x0c 0x65 # CHECK: move16 $3, $5
+0x46 0x3b # CHECK: sdbbp16 8
+0x04 0x3b # CHECK: subu16 $5, $16, $3
+0x44 0xd8 # CHECK: xor16 $17, $5
Modified: llvm/trunk/test/MC/Mips/micromips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/valid.s?rev=250381&r1=250380&r2=250381&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/valid.s Thu Oct 15 03:39:07 2015
@@ -198,3 +198,9 @@
tltu $16, $sp, 15 # CHECK: tltu $16, $sp, 15 # encoding: [0x03,0xb0,0xfa,0x3c]
tne $6, $17 # CHECK: tne $6, $17 # encoding: [0x02,0x26,0x0c,0x3c]
tne $7, $8, 15 # CHECK: tne $7, $8, 15 # encoding: [0x01,0x07,0xfc,0x3c]
+ break16 8 # CHECK: break16 8 # encoding: [0x46,0x1b]
+ li16 $3, -1 # CHECK: li16 $3, -1 # encoding: [0xed,0xff]
+ move16 $3, $5 # CHECK: move16 $3, $5 # encoding: [0x0c,0x65]
+ sdbbp16 8 # CHECK: sdbbp16 8 # encoding: [0x46,0x3b]
+ subu16 $5, $16, $3 # CHECK: subu16 $5, $16, $3 # encoding: [0x04,0x3b]
+ xor16 $17, $5 # CHECK: xor16 $17, $5 # encoding: [0x44,0xd8]
Modified: llvm/trunk/test/MC/Mips/micromips64r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips64r6/valid.s?rev=250381&r1=250380&r2=250381&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips64r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips64r6/valid.s Thu Oct 15 03:39:07 2015
@@ -115,5 +115,11 @@ a:
jalr $9 # CHECK: jalr $9 # encoding: [0x45,0x2b]
jrc16 $9 # CHECK: jrc16 $9 # encoding: [0x45,0x23]
jrcaddiusp 20 # CHECK: jrcaddiusp 20 # encoding: [0x44,0xb3]
+ break16 8 # CHECK: break16 8 # encoding: [0x46,0x1b]
+ li16 $3, -1 # CHECK: li16 $3, -1 # encoding: [0xed,0xff]
+ move16 $3, $5 # CHECK: move16 $3, $5 # encoding: [0x0c,0x65]
+ sdbbp16 8 # CHECK: sdbbp16 8 # encoding: [0x46,0x3b]
+ subu16 $5, $16, $3 # CHECK: subu16 $5, $16, $3 # encoding: [0x04,0x3b]
+ xor16 $17, $5 # CHECK: xor16 $17, $5 # encoding: [0x44,0xd8]
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