[PATCH] D13735: AMDGPU: Fix off by one in register parsing

[Matt Arsenault via llvm-commits]

arsenm created this revision.
arsenm added a reviewer: tstellarAMD.
arsenm added a subscriber: llvm-commits.
Herald added a subscriber: arsenm.

If trying to use one past the end, this would assert.


http://reviews.llvm.org/D13735

Files:
  lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
  test/MC/AMDGPU/out-of-range-registers.s

Index: test/MC/AMDGPU/out-of-range-registers.s
===================================================================
--- /dev/null
+++ test/MC/AMDGPU/out-of-range-registers.s
@@ -0,0 +1,14 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s
+
+s_add_i32 s104, s0, s1
+// CHECK: error: invalid operand for instruction
+
+s_add_i32 s105, s0, s1
+// CHECK: error: invalid operand for instruction
+
+v_add_i32 v256, v0, v1
+// CHECK: error: invalid operand for instruction
+
+v_add_i32 v257, v0, v1
+// CHECK: error: invalid operand for instruction
Index: lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
===================================================================
--- lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -545,11 +545,12 @@
     }
   }
 
-  const MCRegisterInfo *TRC = getContext().getRegisterInfo();
-  unsigned RC = getRegClass(IsVgpr, RegWidth);
-  if (RegIndexInClass > TRC->getRegClass(RC).getNumRegs())
+  const MCRegisterInfo *TRI = getContext().getRegisterInfo();
+  const MCRegisterClass RC = TRI->getRegClass(getRegClass(IsVgpr, RegWidth));
+  if (RegIndexInClass >= RC.getNumRegs())
     return true;
-  RegNo = TRC->getRegClass(RC).getRegister(RegIndexInClass);
+
+  RegNo = RC.getRegister(RegIndexInClass);
   return false;
 }
 


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