[PATCH] D13648: AVX512: shuff62x2 DAG lowering
Elena Demikhovsky via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 14 06:28:21 PDT 2015
delena added inline comments.
================
Comment at: lib/Target/X86/InstPrinter/X86InstComments.cpp:774
@@ -728,2 +773,3 @@
break;
-
+ CASE_ALL_VSHUF64x2_FAMILY(64X2)
+ CASE_ALL_VSHUF64x2_FAMILY(32X4) {
----------------
case_VSHUF(64x2)
case_VSHUF(32x4)
================
Comment at: lib/Target/X86/Utils/X86ShuffleDecode.cpp:273
@@ +272,3 @@
+ unsigned NumLanes = VT.getSizeInBits() / 128;
+ unsigned NumElementsInLane = 128 / VT.getVectorElementType().getSizeInBits();
+ unsigned ControlBitsMask = NumLanes - 1;
----------------
you can use VT.getScalarSizeInBits()
================
Comment at: lib/Target/X86/X86ISelLowering.cpp:10721
@@ +10720,3 @@
+ SelectionDAG &DAG) {
+ assert(VT.getVectorElementType().getSizeInBits() == 64 &&
+ "Unexpected element type size for 128bit shuffle.");
----------------
VT.getScalarSizeInBits()
================
Comment at: lib/Target/X86/X86ISelLowering.cpp:10743
@@ +10742,3 @@
+
+ // Use first element in place of undef musk.
+ Imm = (WidenedMask[i] == SM_SentinelUndef) ? 0 : WidenedMask[i];
----------------
mask
Repository:
rL LLVM
http://reviews.llvm.org/D13648
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