[PATCH] D13660: [x86] Fix wrong lowering of vsetcc nodes (PR25080).

[Andrea Di Biagio via llvm-commits]

andreadb added a comment.

In http://reviews.llvm.org/D13660#265110, @qcolombet wrote:

> Hi Andrea,
>
> LGTM.
>  Could you double check if ARM/AArch64 target may suffer the same kind of assumptions?
>
> Thanks,
> -Quentin


Hi Quentin,

ARM/AArch64 don't seem to suffer for this same problem.
The lowering logic in ARMISelLowering.cpp (function LowerVSETCC) uses the operand type to lower a setcc node. To avoid problems with mismatching return type, it explicitly calls

  DAG.getSExtOrTrunc(Result, dl, VT);   // VT is the setcc return type.

So the transformation for ARM is perfectly okay. I also verified that the reproducible test case doesn't fail to compile using an arm triple.
A similar logic is used in AArch64ISelLowering.cpp (function LowerVSETCC). Even in this case, each call to function 'EmitVectorComparison' is post-dominated by a call to 'getSExtOrTrunc(dl, Cmp, Op.getValueType())'. Here 'Op' is the setcc node, so we are safe.

I hope this helps!

Thanks for the review Quentin!
Cheers,
Andrea


http://reviews.llvm.org/D13660