[PATCH] D13649: [mips] Clang ll/sc illegal instruction on mips64r2 with -O0

[Vasileios Kalintiris via llvm-commits]

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We should choose the correct instruction opcodes inside the function `emitAtomicCmpSwapPartword()` according to the register class that we want to use (see for example the code in function `emitAtomicCmpSwap()`).


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Comment at: lib/Target/Mips/MipsISelLowering.cpp:1415
@@ -1409,3 +1414,3 @@
   MachineRegisterInfo &RegInfo = MF->getRegInfo();
-  const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
+  const TargetRegisterClass *RC = Subtarget.isABI_N64() ? getRegClassFor(MVT::i64) : getRegClassFor(MVT::i32);
   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
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We can use the ternary operator inside the `getRegClassFor` in order to save space. Also, make sure to clang-format the code.

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Comment at: test/CodeGen/Mips/at1.ll:1
@@ +1,2 @@
+; RUN: llc %s   -march=mips64el -mcpu=mips64r2 < %s -filetype=obj -o - \
+; RUN:   | llvm-objdump -mattr=+mips64r2 -d - | FileCheck %s -implicit-check-not=sw
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You use `%s` twice here. We should pick only one method for passing the code to llc.


http://reviews.llvm.org/D13649