[PATCH] D13593: [mips] wrong opcode for ll/sc instructions on mipsr6 when -integrated-as is used
Jelena Losic via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 9 07:20:00 PDT 2015
Jelena.Losic created this revision.
Jelena.Losic added a reviewer: zoran.jovanovic.
Jelena.Losic added a subscriber: llvm-commits.
This commit resolves wrong opcode of instructions ll and sc for r6 architecutres, which was generated in method MipsTargetLowering::emitAtomicBinary.
http://reviews.llvm.org/D13593
Files:
lib/Target/Mips/MipsISelLowering.cpp
test/Object/Mips/at.ll
Index: test/Object/Mips/at.ll
===================================================================
--- test/Object/Mips/at.ll
+++ test/Object/Mips/at.ll
@@ -0,0 +1,16 @@
+; RUN: llc %s -march=mips64el -mcpu=mips64r6 < %s -filetype=obj -o - \
+; RUN: | llvm-objdump -mattr=+mips64r6 -d - | grep sc
+
+
+define internal i32 @atomic_load_test() #0 {
+entry:
+
+ %load_add = alloca i32*, align 8
+ %.atomicdst = alloca i32, align 4
+ %0 = load i32*, i32** %load_add, align 8
+ %1 = load atomic i32, i32* %0 acquire, align 4
+ store i32 %1, i32* %.atomicdst, align 4
+ %2 = load i32, i32* %.atomicdst, align 4
+
+ ret i32 %2
+}
\ No newline at end of file
Index: lib/Target/Mips/MipsISelLowering.cpp
===================================================================
--- lib/Target/Mips/MipsISelLowering.cpp
+++ lib/Target/Mips/MipsISelLowering.cpp
@@ -1331,14 +1331,19 @@
unsigned LL, SC, ZERO, BNE, BEQ;
if (Size == 4) {
- LL = isMicroMips ? Mips::LL_MM : Mips::LL;
- SC = isMicroMips ? Mips::SC_MM : Mips::SC;
+ if (isMicroMips) {
+ LL = Mips::LL_MM;
+ SC = Mips::SC_MM;
+ } else {
+ LL = Subtarget.hasMips32r6() ? Mips::LL_R6 : Mips::LL;
+ SC = Subtarget.hasMips32r6() ? Mips::SC_R6 : Mips::SC;
+ }
ZERO = Mips::ZERO;
BNE = Mips::BNE;
BEQ = Mips::BEQ;
} else {
- LL = Mips::LLD;
- SC = Mips::SCD;
+ LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
+ SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
ZERO = Mips::ZERO_64;
BNE = Mips::BNE64;
BEQ = Mips::BEQ64;
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