[PATCH] D13466: [AArch64] Implement vector splitting on UADDV.

[Charlie Turner via llvm-commits]

chatur01 updated this revision to Diff 36751.
chatur01 added a comment.

Thanks Jun & James for the reviews!

I've added support for SADDV, [SU]{MAX,MIN}V.

> do we support FMINV and friends yet?


Doesn't look like it.

> Please also add a testcase that shows this works when more than one split is required; <16 x i32> for example.


There's some missing patterns for ADDV that prevents me from testing this. I raised https://llvm.org/bugs/show_bug.cgi?id=25093

The SADDV / UADDV distinction looks a bit superficial to me, so ISD::ADD is used in both cases. We don't have a sign distinction in the architecture for ADDV, so I don't know why we have two nodes for them.

I'll update the commit title when it lands to reflect the wider scope.


http://reviews.llvm.org/D13466

Files:
  lib/Target/AArch64/AArch64ISelLowering.cpp
  test/CodeGen/AArch64/aarch64-addv.ll
  test/CodeGen/AArch64/aarch64-minmaxv.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D13466.36751.patch
Type: text/x-patch
Size: 13023 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20151007/6743c57c/attachment.bin>