[PATCH] D13442: [AArch64] Fold vector fmul/fdiv by pow2 into floating-point/fixed-point conversions.

[Chad Rosier via llvm-commits]

mcrosier added a comment.

Thanks, Tim.  I'll post a new revision in a bit.


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Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:7538
@@ +7537,3 @@
+// elements are the same constant, C, and Log2(C) ranges from 1 to Range.
+static bool isConstVecPow2(SDValue ConstVec, bool IsSigned, uint64_t &C,
+                           unsigned Range) {
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t.p.northover wrote:
> I've just noticed this started life in ARMISelLowering.cpp; since we're improving it here, can we fix that one too? Or even share the implementation somewhere (BuildVectorSDNode, or perhaps SelectionDAG if you anticipate handling more cases in the future)
I was planning on updating the version in ARMISelLowering as well, but I agree we can just make this common to BuildVectorSDNode or elsewhere and use the new version in both ARM and AArch64.

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Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:7543
@@ +7542,3 @@
+    ConstantFPSDNode *CN = BV->getConstantFPSplatNode(&UndefElements);
+    if (!CN || !UndefElements.none())
+      return false;
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t.p.northover wrote:
> Why are we bailing on undef here?
No particular reason other than I was trying to be conservative.  I'll remove the !UndefElements.none() check.

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Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:7549
@@ +7548,3 @@
+    APFloat APF = CN->getValueAPF();
+    if (APF.convertToInteger(&C0, 64, IsSigned, APFloat::rmTowardZero, &IsExact) != APFloat::opOK || !IsExact)
+      return false;
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t.p.northover wrote:
> I don't think this can handle 2^64. Really, we might as well convert to an APSInt and use exactLogBase2 or something.
Thanks for the suggestion, Tim.  I'm not overly familiar with all of the APFloat/APInt APIs, hence the less than ideal solution.  I'll start digging to see if I can't implement a more robust solution.


http://reviews.llvm.org/D13442