[PATCH] D13447: [AArch64]Fix bug in DAG combine for ADDV

[James Molloy via llvm-commits]

Yes. This occurs for all other ISD nodes, see what happens for example if
you try a v8i32 ADD.
On Mon, 5 Oct 2015 at 22:07, Jun Bum Lim via llvm-commits <
llvm-commits at lists.llvm.org> wrote:

> junbuml added a comment.
>
> Do you mean combining for oversized input vector for ADDV could be
> combined, but it should be legalized after then by splitting the vector ?
>
>
> http://reviews.llvm.org/D13447
>
>
>
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