[llvm] r249378 - [TwoAddressInstructionPass] When looking for a 3 addr conversion after commuting, make sure regB has been updated to take into account the commute.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Tue Oct  6 00:39:59 2015
New Revision: 249378

URL: http://llvm.org/viewvc/llvm-project?rev=249378&view=rev
Log:
[TwoAddressInstructionPass] When looking for a 3 addr conversion after commuting, make sure regB has been updated to take into account the commute.

Modified:
    llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
    llvm/trunk/test/CodeGen/X86/atomic_mi.ll
    llvm/trunk/test/CodeGen/X86/commute-two-addr.ll
    llvm/trunk/test/Transforms/LoopStrengthReduce/X86/ivchain-stress-X86.ll

Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=249378&r1=249377&r2=249378&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Tue Oct  6 00:39:59 2015
@@ -1265,6 +1265,13 @@ tryInstructionTransform(MachineBasicBloc
     return true;
   }
 
+  // If we commuted, regB may have changed so we should re-sample it to avoid
+  // confusing the three address conversion below.
+  if (Commuted) {
+    regB = MI.getOperand(SrcIdx).getReg();
+    regBKilled = isKilled(MI, regB, MRI, TII, LIS, true);
+  }
+
   if (MI.isConvertibleTo3Addr()) {
     // This instruction is potentially convertible to a true
     // three-address instruction.  Check if it is profitable.

Modified: llvm/trunk/test/CodeGen/X86/atomic_mi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/atomic_mi.ll?rev=249378&r1=249377&r2=249378&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/atomic_mi.ll (original)
+++ llvm/trunk/test/CodeGen/X86/atomic_mi.ll Tue Oct  6 00:39:59 2015
@@ -210,8 +210,8 @@ define i32 @add_32r_ret_load(i32* %p, i3
 ; X64-LABEL: add_32r_ret_load:
 ; X64-NOT: lock
 ; X64:      movl (%rdi), %eax
-; X64-NEXT: leal (%rsi,%rax), %ecx
-; X64-NEXT: movl %ecx, (%rdi)
+; X64-NEXT: addl %eax, %esi
+; X64-NEXT: movl %esi, (%rdi)
 ; X64-NEXT: retq
 ; X32-LABEL: add_32r_ret_load:
 ; X32-NOT: lock

Modified: llvm/trunk/test/CodeGen/X86/commute-two-addr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/commute-two-addr.ll?rev=249378&r1=249377&r2=249378&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/commute-two-addr.ll (original)
+++ llvm/trunk/test/CodeGen/X86/commute-two-addr.ll Tue Oct  6 00:39:59 2015
@@ -39,7 +39,7 @@ define %0 @t3(i32 %lb, i8 zeroext %has_l
 entry:
 ; DARWIN-LABEL: t3:
 ; DARWIN: shlq $32, %rcx
-; DARWIN-NEXT: leaq (%rax,%rcx), %rax
+; DARWIN-NEXT: orq %rcx, %rax
 ; DARWIN-NEXT: shll $8
 ; DARWIN-NOT: leaq
   %tmp21 = zext i32 %lb to i64

Modified: llvm/trunk/test/Transforms/LoopStrengthReduce/X86/ivchain-stress-X86.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/X86/ivchain-stress-X86.ll?rev=249378&r1=249377&r2=249378&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/LoopStrengthReduce/X86/ivchain-stress-X86.ll (original)
+++ llvm/trunk/test/Transforms/LoopStrengthReduce/X86/ivchain-stress-X86.ll Tue Oct  6 00:39:59 2015
@@ -23,7 +23,7 @@
 ; X32: add
 ; X32: add
 ; X32: add
-; X32: leal
+; X32: add
 ; X32: %for.body.3
 define void @sharedidx(i8* nocapture %a, i8* nocapture %b, i8* nocapture %c, i32 %s, i32 %len) nounwind ssp {
 entry: