[PATCH] D13239: [ARM] Modify codegen for memcpy intrinsic to prefer LDM/STM.

[Tim Northover via llvm-commits]

t.p.northover added a subscriber: t.p.northover.
t.p.northover added a comment.

Definitely a good idea on the whole.


================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:8097-8098
@@ +8096,4 @@
+
+  // The MEMCPY both defines and kills the scratch registers.  We have
+  // to do the kills in a second MI.
+  const ARMBaseInstrInfo *TII = Subtarget->getInstrInfo();
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Why's the second MI needed? Does regalloc not bother to allocate <def,dead> operands or something?

================
Comment at: lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp:753-754
@@ +752,4 @@
+  std::vector<MCOperand> RegOps(MI->begin() + OpNum, MI->end());
+  std::stable_sort(RegOps.begin(), RegOps.end(),
+                   [this](const MCOperand &O1, const MCOperand &O2) -> bool {
+                     return MRI.getEncodingValue(O1.getReg()) <
----------------
I think it'd be better to do the sorting when the instruction is expanded, it seems like a useful property to have if anyone wants to analyse an LDM/STM.


http://reviews.llvm.org/D13239