[PATCH] D13278: [SLP] Add -slp-min-reg-size command line option.

[Michael Zolotukhin via llvm-commits]

mzolotukhin created this revision.
mzolotukhin added reviewers: aschwaighofer, nadav, hfinkel.
mzolotukhin added a subscriber: llvm-commits.

MinVecRegSize is currently hardcoded to 128; this patch adds a cl::opt to allow
changing it. I tried not to change any existing behavior for the default case.

This option would be handy for writing smaller tests. Also, currently it's not
even possible to write a test for vectorization of i1/i2/i4 stores, as we only
look for at most 16 accesses, while the minimal total size should be 128bits.
It's possible to write such test using phi-nodes, but that looks like a bug (I
plan to follow up with a fix for it too).

http://reviews.llvm.org/D13278

Files:
  lib/Transforms/Vectorize/SLPVectorizer.cpp

Index: lib/Transforms/Vectorize/SLPVectorizer.cpp
===================================================================
--- lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -73,11 +73,13 @@
 MaxVectorRegSizeOption("slp-max-reg-size", cl::init(128), cl::Hidden,
     cl::desc("Attempt to vectorize for this register size in bits"));
 
+static cl::opt<int>
+MinVectorRegSizeOption("slp-min-reg-size", cl::init(128), cl::Hidden,
+    cl::desc("Attempt to vectorize for this register size in bits"));
+
 namespace {
 
 // FIXME: Set this via cl::opt to allow overriding.
-static const unsigned MinVecRegSize = 128;
-
 static const unsigned RecursionMaxDepth = 12;
 
 // Limit the number of alias checks. The limit is chosen so that
@@ -3107,6 +3109,8 @@
     else
       MaxVecRegSize = TTI->getRegisterBitWidth(true);
 
+    MinVecRegSize = MinVectorRegSizeOption;
+
     // Don't vectorize when the attribute NoImplicitFloat is used.
     if (F.hasFnAttribute(Attribute::NoImplicitFloat))
       return false;
@@ -3191,6 +3195,7 @@
 private:
   StoreListMap StoreRefs;
   unsigned MaxVecRegSize; // This is set by TTI or overridden by cl::opt.
+  unsigned MinVecRegSize; // Set by by cl::opt (default: 128).
 };
 
 /// \brief Check that the Values in the slice in VL array are still existent in
@@ -3574,10 +3579,13 @@
   /// splits the vector in halves and adds those halves.
   bool IsPairwiseReduction;
 
+  unsigned MinVecRegSize;
+
 public:
-  HorizontalReduction()
-    : ReductionRoot(nullptr), ReductionPHI(nullptr), ReductionOpcode(0),
-    ReducedValueOpcode(0), ReduxWidth(0), IsPairwiseReduction(false) {}
+  HorizontalReduction(unsigned MinRegSize)
+      : ReductionRoot(nullptr), ReductionPHI(nullptr), ReductionOpcode(0),
+        ReducedValueOpcode(0), ReduxWidth(0), IsPairwiseReduction(false),
+        MinVecRegSize(MinRegSize) {}
 
   /// \brief Try to find a reduction tree.
   bool matchAssociativeReduction(PHINode *Phi, BinaryOperator *B) {
@@ -3919,7 +3927,7 @@
         continue;
 
       // Try to match and vectorize a horizontal reduction.
-      HorizontalReduction HorRdx;
+      HorizontalReduction HorRdx(MinVecRegSize);
       if (ShouldVectorizeHor && HorRdx.matchAssociativeReduction(P, BI) &&
           HorRdx.tryToReduce(R, TTI)) {
         Changed = true;
@@ -3949,7 +3957,7 @@
       if (StoreInst *SI = dyn_cast<StoreInst>(it))
         if (BinaryOperator *BinOp =
                 dyn_cast<BinaryOperator>(SI->getValueOperand())) {
-          HorizontalReduction HorRdx;
+          HorizontalReduction HorRdx(MinVecRegSize);
           if (((HorRdx.matchAssociativeReduction(nullptr, BinOp) &&
                 HorRdx.tryToReduce(R, TTI)) ||
                tryToVectorize(BinOp, R))) {


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