[PATCH] D13239: [ARM] Modify codegen for memcpy intrinsic to prefer LDM/STM.

[scott douglass via llvm-commits]

scott-0 created this revision.
scott-0 added a reviewer: pcc.
scott-0 added a subscriber: llvm-commits.
Herald added subscribers: rengolin, aemerson.

We were previously codegen'ing memcpy as regular load/store operations and
hoping that the register allocator would allocate registers in ascending order
so that we could apply an LDM/STM combine after register allocation. According
to the commit that first introduced this code (r37179), we planned to teach
the register allocator to allocate the registers in ascending order. This
never got implemented, and up to now we've been stuck with very poor codegen.

A much simpler approach for achieving better codegen is to create MCOPY pseudo
instructions, attach scratch virtual registers to them and then, post register
allocation, expand the MCOPYs into LDM/STM pairs using the scratch registers.
The register allocator will pick arbitrary registers which we will sort when
printing the MCInst. This approach also avoids the need to repeatedly
calculate offsets which ultimately ought to be eliminated pre-RA in order to
decrease register pressure.

Fixes PR9199 and PR23768.

[This is based on Peter Collingbourne's r238473 which was reverted.  I'm happy to produce the diff from r238473 if that's helpful.]


http://reviews.llvm.org/D13239

Files:
  lib/Target/ARM/ARMBaseInstrInfo.cpp
  lib/Target/ARM/ARMBaseInstrInfo.h
  lib/Target/ARM/ARMISelLowering.cpp
  lib/Target/ARM/ARMISelLowering.h
  lib/Target/ARM/ARMInstrInfo.td
  lib/Target/ARM/ARMInstrThumb.td
  lib/Target/ARM/ARMSelectionDAGInfo.cpp
  lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
  lib/Target/ARM/Thumb2SizeReduction.cpp
  test/CodeGen/ARM/load-store-flags.ll
  test/CodeGen/Thumb/ldm-stm-base-materialization.ll
  test/CodeGen/Thumb/thumb-memcpy-ldm-stm.ll

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