[llvm] r248672 - [InstCombine] Removed unnecessary meta attributes.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sat Sep 26 10:49:04 PDT 2015
Author: rksimon
Date: Sat Sep 26 12:49:04 2015
New Revision: 248672
URL: http://llvm.org/viewvc/llvm-project?rev=248672&view=rev
Log:
[InstCombine] Removed unnecessary meta attributes.
Modified:
llvm/trunk/test/Transforms/InstCombine/x86-vector-shifts.ll
Modified: llvm/trunk/test/Transforms/InstCombine/x86-vector-shifts.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/x86-vector-shifts.ll?rev=248672&r1=248671&r2=248672&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/x86-vector-shifts.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/x86-vector-shifts.ll Sat Sep 26 12:49:04 2015
@@ -5,14 +5,14 @@ target datalayout = "e-m:e-i64:64-f80:12
; ASHR - Immediate
;
-define <8 x i16> @sse2_psrai_w_0(<8 x i16> %v) nounwind readnone uwtable {
+define <8 x i16> @sse2_psrai_w_0(<8 x i16> %v) {
; CHECK-LABEL: @sse2_psrai_w_0
; CHECK-NEXT: ret <8 x i16> %v
%1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %v, i32 0)
ret <8 x i16> %1
}
-define <8 x i16> @sse2_psrai_w_15(<8 x i16> %v) nounwind readnone uwtable {
+define <8 x i16> @sse2_psrai_w_15(<8 x i16> %v) {
; CHECK-LABEL: @sse2_psrai_w_15
; CHECK-NEXT: %1 = ashr <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
; CHECK-NEXT: ret <8 x i16> %1
@@ -20,7 +20,7 @@ define <8 x i16> @sse2_psrai_w_15(<8 x i
ret <8 x i16> %1
}
-define <8 x i16> @sse2_psrai_w_64(<8 x i16> %v) nounwind readnone uwtable {
+define <8 x i16> @sse2_psrai_w_64(<8 x i16> %v) {
; CHECK-LABEL: @sse2_psrai_w_64
; CHECK-NEXT: %1 = ashr <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
; CHECK-NEXT: ret <8 x i16> %1
@@ -28,14 +28,14 @@ define <8 x i16> @sse2_psrai_w_64(<8 x i
ret <8 x i16> %1
}
-define <4 x i32> @sse2_psrai_d_0(<4 x i32> %v) nounwind readnone uwtable {
+define <4 x i32> @sse2_psrai_d_0(<4 x i32> %v) {
; CHECK-LABEL: @sse2_psrai_d_0
; CHECK-NEXT: ret <4 x i32> %v
%1 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %v, i32 0)
ret <4 x i32> %1
}
-define <4 x i32> @sse2_psrai_d_15(<4 x i32> %v) nounwind readnone uwtable {
+define <4 x i32> @sse2_psrai_d_15(<4 x i32> %v) {
; CHECK-LABEL: @sse2_psrai_d_15
; CHECK-NEXT: %1 = ashr <4 x i32> %v, <i32 15, i32 15, i32 15, i32 15>
; CHECK-NEXT: ret <4 x i32> %1
@@ -43,7 +43,7 @@ define <4 x i32> @sse2_psrai_d_15(<4 x i
ret <4 x i32> %1
}
-define <4 x i32> @sse2_psrai_d_64(<4 x i32> %v) nounwind readnone uwtable {
+define <4 x i32> @sse2_psrai_d_64(<4 x i32> %v) {
; CHECK-LABEL: @sse2_psrai_d_64
; CHECK-NEXT: %1 = ashr <4 x i32> %v, <i32 31, i32 31, i32 31, i32 31>
; CHECK-NEXT: ret <4 x i32> %1
@@ -51,14 +51,14 @@ define <4 x i32> @sse2_psrai_d_64(<4 x i
ret <4 x i32> %1
}
-define <16 x i16> @avx2_psrai_w_0(<16 x i16> %v) nounwind readnone uwtable {
+define <16 x i16> @avx2_psrai_w_0(<16 x i16> %v) {
; CHECK-LABEL: @avx2_psrai_w_0
; CHECK-NEXT: ret <16 x i16> %v
%1 = tail call <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16> %v, i32 0)
ret <16 x i16> %1
}
-define <16 x i16> @avx2_psrai_w_15(<16 x i16> %v) nounwind readnone uwtable {
+define <16 x i16> @avx2_psrai_w_15(<16 x i16> %v) {
; CHECK-LABEL: @avx2_psrai_w_15
; CHECK-NEXT: %1 = ashr <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
; CHECK-NEXT: ret <16 x i16> %1
@@ -66,7 +66,7 @@ define <16 x i16> @avx2_psrai_w_15(<16 x
ret <16 x i16> %1
}
-define <16 x i16> @avx2_psrai_w_64(<16 x i16> %v) nounwind readnone uwtable {
+define <16 x i16> @avx2_psrai_w_64(<16 x i16> %v) {
; CHECK-LABEL: @avx2_psrai_w_64
; CHECK-NEXT: %1 = ashr <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
; CHECK-NEXT: ret <16 x i16> %1
@@ -74,14 +74,14 @@ define <16 x i16> @avx2_psrai_w_64(<16 x
ret <16 x i16> %1
}
-define <8 x i32> @avx2_psrai_d_0(<8 x i32> %v) nounwind readnone uwtable {
+define <8 x i32> @avx2_psrai_d_0(<8 x i32> %v) {
; CHECK-LABEL: @avx2_psrai_d_0
; CHECK-NEXT: ret <8 x i32> %v
%1 = tail call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> %v, i32 0)
ret <8 x i32> %1
}
-define <8 x i32> @avx2_psrai_d_15(<8 x i32> %v) nounwind readnone uwtable {
+define <8 x i32> @avx2_psrai_d_15(<8 x i32> %v) {
; CHECK-LABEL: @avx2_psrai_d_15
; CHECK-NEXT: %1 = ashr <8 x i32> %v, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
; CHECK-NEXT: ret <8 x i32> %1
@@ -89,7 +89,7 @@ define <8 x i32> @avx2_psrai_d_15(<8 x i
ret <8 x i32> %1
}
-define <8 x i32> @avx2_psrai_d_64(<8 x i32> %v) nounwind readnone uwtable {
+define <8 x i32> @avx2_psrai_d_64(<8 x i32> %v) {
; CHECK-LABEL: @avx2_psrai_d_64
; CHECK-NEXT: %1 = ashr <8 x i32> %v, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
; CHECK-NEXT: ret <8 x i32> %1
@@ -101,14 +101,14 @@ define <8 x i32> @avx2_psrai_d_64(<8 x i
; LSHR - Immediate
;
-define <8 x i16> @sse2_psrli_w_0(<8 x i16> %v) nounwind readnone uwtable {
+define <8 x i16> @sse2_psrli_w_0(<8 x i16> %v) {
; CHECK-LABEL: @sse2_psrli_w_0
; CHECK-NEXT: ret <8 x i16> %v
%1 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %v, i32 0)
ret <8 x i16> %1
}
-define <8 x i16> @sse2_psrli_w_15(<8 x i16> %v) nounwind readnone uwtable {
+define <8 x i16> @sse2_psrli_w_15(<8 x i16> %v) {
; CHECK-LABEL: @sse2_psrli_w_15
; CHECK-NEXT: %1 = lshr <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
; CHECK-NEXT: ret <8 x i16> %1
@@ -116,21 +116,21 @@ define <8 x i16> @sse2_psrli_w_15(<8 x i
ret <8 x i16> %1
}
-define <8 x i16> @sse2_psrli_w_64(<8 x i16> %v) nounwind readnone uwtable {
+define <8 x i16> @sse2_psrli_w_64(<8 x i16> %v) {
; CHECK-LABEL: @sse2_psrli_w_64
; CHECK-NEXT: ret <8 x i16> zeroinitializer
%1 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %v, i32 64)
ret <8 x i16> %1
}
-define <4 x i32> @sse2_psrli_d_0(<4 x i32> %v) nounwind readnone uwtable {
+define <4 x i32> @sse2_psrli_d_0(<4 x i32> %v) {
; CHECK-LABEL: @sse2_psrli_d_0
; CHECK-NEXT: ret <4 x i32> %v
%1 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %v, i32 0)
ret <4 x i32> %1
}
-define <4 x i32> @sse2_psrli_d_15(<4 x i32> %v) nounwind readnone uwtable {
+define <4 x i32> @sse2_psrli_d_15(<4 x i32> %v) {
; CHECK-LABEL: @sse2_psrli_d_15
; CHECK-NEXT: %1 = lshr <4 x i32> %v, <i32 15, i32 15, i32 15, i32 15>
; CHECK-NEXT: ret <4 x i32> %1
@@ -138,21 +138,21 @@ define <4 x i32> @sse2_psrli_d_15(<4 x i
ret <4 x i32> %1
}
-define <4 x i32> @sse2_psrli_d_64(<4 x i32> %v) nounwind readnone uwtable {
+define <4 x i32> @sse2_psrli_d_64(<4 x i32> %v) {
; CHECK-LABEL: @sse2_psrli_d_64
; CHECK-NEXT: ret <4 x i32> zeroinitializer
%1 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %v, i32 64)
ret <4 x i32> %1
}
-define <2 x i64> @sse2_psrli_q_0(<2 x i64> %v) nounwind readnone uwtable {
+define <2 x i64> @sse2_psrli_q_0(<2 x i64> %v) {
; CHECK-LABEL: @sse2_psrli_q_0
; CHECK-NEXT: ret <2 x i64> %v
%1 = tail call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> %v, i32 0)
ret <2 x i64> %1
}
-define <2 x i64> @sse2_psrli_q_15(<2 x i64> %v) nounwind readnone uwtable {
+define <2 x i64> @sse2_psrli_q_15(<2 x i64> %v) {
; CHECK-LABEL: @sse2_psrli_q_15
; CHECK-NEXT: %1 = lshr <2 x i64> %v, <i64 15, i64 15>
; CHECK-NEXT: ret <2 x i64> %1
@@ -160,21 +160,21 @@ define <2 x i64> @sse2_psrli_q_15(<2 x i
ret <2 x i64> %1
}
-define <2 x i64> @sse2_psrli_q_64(<2 x i64> %v) nounwind readnone uwtable {
+define <2 x i64> @sse2_psrli_q_64(<2 x i64> %v) {
; CHECK-LABEL: @sse2_psrli_q_64
; CHECK-NEXT: ret <2 x i64> zeroinitializer
%1 = tail call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> %v, i32 64)
ret <2 x i64> %1
}
-define <16 x i16> @avx2_psrli_w_0(<16 x i16> %v) nounwind readnone uwtable {
+define <16 x i16> @avx2_psrli_w_0(<16 x i16> %v) {
; CHECK-LABEL: @avx2_psrli_w_0
; CHECK-NEXT: ret <16 x i16> %v
%1 = tail call <16 x i16> @llvm.x86.avx2.psrli.w(<16 x i16> %v, i32 0)
ret <16 x i16> %1
}
-define <16 x i16> @avx2_psrli_w_15(<16 x i16> %v) nounwind readnone uwtable {
+define <16 x i16> @avx2_psrli_w_15(<16 x i16> %v) {
; CHECK-LABEL: @avx2_psrli_w_15
; CHECK-NEXT: %1 = lshr <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
; CHECK-NEXT: ret <16 x i16> %1
@@ -182,21 +182,21 @@ define <16 x i16> @avx2_psrli_w_15(<16 x
ret <16 x i16> %1
}
-define <16 x i16> @avx2_psrli_w_64(<16 x i16> %v) nounwind readnone uwtable {
+define <16 x i16> @avx2_psrli_w_64(<16 x i16> %v) {
; CHECK-LABEL: @avx2_psrli_w_64
; CHECK-NEXT: ret <16 x i16> zeroinitializer
%1 = tail call <16 x i16> @llvm.x86.avx2.psrli.w(<16 x i16> %v, i32 64)
ret <16 x i16> %1
}
-define <8 x i32> @avx2_psrli_d_0(<8 x i32> %v) nounwind readnone uwtable {
+define <8 x i32> @avx2_psrli_d_0(<8 x i32> %v) {
; CHECK-LABEL: @avx2_psrli_d_0
; CHECK-NEXT: ret <8 x i32> %v
%1 = tail call <8 x i32> @llvm.x86.avx2.psrli.d(<8 x i32> %v, i32 0)
ret <8 x i32> %1
}
-define <8 x i32> @avx2_psrli_d_15(<8 x i32> %v) nounwind readnone uwtable {
+define <8 x i32> @avx2_psrli_d_15(<8 x i32> %v) {
; CHECK-LABEL: @avx2_psrli_d_15
; CHECK-NEXT: %1 = lshr <8 x i32> %v, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
; CHECK-NEXT: ret <8 x i32> %1
@@ -204,21 +204,21 @@ define <8 x i32> @avx2_psrli_d_15(<8 x i
ret <8 x i32> %1
}
-define <8 x i32> @avx2_psrli_d_64(<8 x i32> %v) nounwind readnone uwtable {
+define <8 x i32> @avx2_psrli_d_64(<8 x i32> %v) {
; CHECK-LABEL: @avx2_psrli_d_64
; CHECK-NEXT: ret <8 x i32> zeroinitializer
%1 = tail call <8 x i32> @llvm.x86.avx2.psrli.d(<8 x i32> %v, i32 64)
ret <8 x i32> %1
}
-define <4 x i64> @avx2_psrli_q_0(<4 x i64> %v) nounwind readnone uwtable {
+define <4 x i64> @avx2_psrli_q_0(<4 x i64> %v) {
; CHECK-LABEL: @avx2_psrli_q_0
; CHECK-NEXT: ret <4 x i64> %v
%1 = tail call <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64> %v, i32 0)
ret <4 x i64> %1
}
-define <4 x i64> @avx2_psrli_q_15(<4 x i64> %v) nounwind readnone uwtable {
+define <4 x i64> @avx2_psrli_q_15(<4 x i64> %v) {
; CHECK-LABEL: @avx2_psrli_q_15
; CHECK-NEXT: %1 = lshr <4 x i64> %v, <i64 15, i64 15, i64 15, i64 15>
; CHECK-NEXT: ret <4 x i64> %1
@@ -226,7 +226,7 @@ define <4 x i64> @avx2_psrli_q_15(<4 x i
ret <4 x i64> %1
}
-define <4 x i64> @avx2_psrli_q_64(<4 x i64> %v) nounwind readnone uwtable {
+define <4 x i64> @avx2_psrli_q_64(<4 x i64> %v) {
; CHECK-LABEL: @avx2_psrli_q_64
; CHECK-NEXT: ret <4 x i64> zeroinitializer
%1 = tail call <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64> %v, i32 64)
@@ -237,14 +237,14 @@ define <4 x i64> @avx2_psrli_q_64(<4 x i
; SHL - Immediate
;
-define <8 x i16> @sse2_pslli_w_0(<8 x i16> %v) nounwind readnone uwtable {
+define <8 x i16> @sse2_pslli_w_0(<8 x i16> %v) {
; CHECK-LABEL: @sse2_pslli_w_0
; CHECK-NEXT: ret <8 x i16> %v
%1 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %v, i32 0)
ret <8 x i16> %1
}
-define <8 x i16> @sse2_pslli_w_15(<8 x i16> %v) nounwind readnone uwtable {
+define <8 x i16> @sse2_pslli_w_15(<8 x i16> %v) {
; CHECK-LABEL: @sse2_pslli_w_15
; CHECK-NEXT: %1 = shl <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
; CHECK-NEXT: ret <8 x i16> %1
@@ -252,21 +252,21 @@ define <8 x i16> @sse2_pslli_w_15(<8 x i
ret <8 x i16> %1
}
-define <8 x i16> @sse2_pslli_w_64(<8 x i16> %v) nounwind readnone uwtable {
+define <8 x i16> @sse2_pslli_w_64(<8 x i16> %v) {
; CHECK-LABEL: @sse2_pslli_w_64
; CHECK-NEXT: ret <8 x i16> zeroinitializer
%1 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %v, i32 64)
ret <8 x i16> %1
}
-define <4 x i32> @sse2_pslli_d_0(<4 x i32> %v) nounwind readnone uwtable {
+define <4 x i32> @sse2_pslli_d_0(<4 x i32> %v) {
; CHECK-LABEL: @sse2_pslli_d_0
; CHECK-NEXT: ret <4 x i32> %v
%1 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %v, i32 0)
ret <4 x i32> %1
}
-define <4 x i32> @sse2_pslli_d_15(<4 x i32> %v) nounwind readnone uwtable {
+define <4 x i32> @sse2_pslli_d_15(<4 x i32> %v) {
; CHECK-LABEL: @sse2_pslli_d_15
; CHECK-NEXT: %1 = shl <4 x i32> %v, <i32 15, i32 15, i32 15, i32 15>
; CHECK-NEXT: ret <4 x i32> %1
@@ -274,21 +274,21 @@ define <4 x i32> @sse2_pslli_d_15(<4 x i
ret <4 x i32> %1
}
-define <4 x i32> @sse2_pslli_d_64(<4 x i32> %v) nounwind readnone uwtable {
+define <4 x i32> @sse2_pslli_d_64(<4 x i32> %v) {
; CHECK-LABEL: @sse2_pslli_d_64
; CHECK-NEXT: ret <4 x i32> zeroinitializer
%1 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %v, i32 64)
ret <4 x i32> %1
}
-define <2 x i64> @sse2_pslli_q_0(<2 x i64> %v) nounwind readnone uwtable {
+define <2 x i64> @sse2_pslli_q_0(<2 x i64> %v) {
; CHECK-LABEL: @sse2_pslli_q_0
; CHECK-NEXT: ret <2 x i64> %v
%1 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> %v, i32 0)
ret <2 x i64> %1
}
-define <2 x i64> @sse2_pslli_q_15(<2 x i64> %v) nounwind readnone uwtable {
+define <2 x i64> @sse2_pslli_q_15(<2 x i64> %v) {
; CHECK-LABEL: @sse2_pslli_q_15
; CHECK-NEXT: %1 = shl <2 x i64> %v, <i64 15, i64 15>
; CHECK-NEXT: ret <2 x i64> %1
@@ -296,21 +296,21 @@ define <2 x i64> @sse2_pslli_q_15(<2 x i
ret <2 x i64> %1
}
-define <2 x i64> @sse2_pslli_q_64(<2 x i64> %v) nounwind readnone uwtable {
+define <2 x i64> @sse2_pslli_q_64(<2 x i64> %v) {
; CHECK-LABEL: @sse2_pslli_q_64
; CHECK-NEXT: ret <2 x i64> zeroinitializer
%1 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> %v, i32 64)
ret <2 x i64> %1
}
-define <16 x i16> @avx2_pslli_w_0(<16 x i16> %v) nounwind readnone uwtable {
+define <16 x i16> @avx2_pslli_w_0(<16 x i16> %v) {
; CHECK-LABEL: @avx2_pslli_w_0
; CHECK-NEXT: ret <16 x i16> %v
%1 = tail call <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16> %v, i32 0)
ret <16 x i16> %1
}
-define <16 x i16> @avx2_pslli_w_15(<16 x i16> %v) nounwind readnone uwtable {
+define <16 x i16> @avx2_pslli_w_15(<16 x i16> %v) {
; CHECK-LABEL: @avx2_pslli_w_15
; CHECK-NEXT: %1 = shl <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
; CHECK-NEXT: ret <16 x i16> %1
@@ -318,21 +318,21 @@ define <16 x i16> @avx2_pslli_w_15(<16 x
ret <16 x i16> %1
}
-define <16 x i16> @avx2_pslli_w_64(<16 x i16> %v) nounwind readnone uwtable {
+define <16 x i16> @avx2_pslli_w_64(<16 x i16> %v) {
; CHECK-LABEL: @avx2_pslli_w_64
; CHECK-NEXT: ret <16 x i16> zeroinitializer
%1 = tail call <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16> %v, i32 64)
ret <16 x i16> %1
}
-define <8 x i32> @avx2_pslli_d_0(<8 x i32> %v) nounwind readnone uwtable {
+define <8 x i32> @avx2_pslli_d_0(<8 x i32> %v) {
; CHECK-LABEL: @avx2_pslli_d_0
; CHECK-NEXT: ret <8 x i32> %v
%1 = tail call <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32> %v, i32 0)
ret <8 x i32> %1
}
-define <8 x i32> @avx2_pslli_d_15(<8 x i32> %v) nounwind readnone uwtable {
+define <8 x i32> @avx2_pslli_d_15(<8 x i32> %v) {
; CHECK-LABEL: @avx2_pslli_d_15
; CHECK-NEXT: %1 = shl <8 x i32> %v, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
; CHECK-NEXT: ret <8 x i32> %1
@@ -340,21 +340,21 @@ define <8 x i32> @avx2_pslli_d_15(<8 x i
ret <8 x i32> %1
}
-define <8 x i32> @avx2_pslli_d_64(<8 x i32> %v) nounwind readnone uwtable {
+define <8 x i32> @avx2_pslli_d_64(<8 x i32> %v) {
; CHECK-LABEL: @avx2_pslli_d_64
; CHECK-NEXT: ret <8 x i32> zeroinitializer
%1 = tail call <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32> %v, i32 64)
ret <8 x i32> %1
}
-define <4 x i64> @avx2_pslli_q_0(<4 x i64> %v) nounwind readnone uwtable {
+define <4 x i64> @avx2_pslli_q_0(<4 x i64> %v) {
; CHECK-LABEL: @avx2_pslli_q_0
; CHECK-NEXT: ret <4 x i64> %v
%1 = tail call <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64> %v, i32 0)
ret <4 x i64> %1
}
-define <4 x i64> @avx2_pslli_q_15(<4 x i64> %v) nounwind readnone uwtable {
+define <4 x i64> @avx2_pslli_q_15(<4 x i64> %v) {
; CHECK-LABEL: @avx2_pslli_q_15
; CHECK-NEXT: %1 = shl <4 x i64> %v, <i64 15, i64 15, i64 15, i64 15>
; CHECK-NEXT: ret <4 x i64> %1
@@ -362,7 +362,7 @@ define <4 x i64> @avx2_pslli_q_15(<4 x i
ret <4 x i64> %1
}
-define <4 x i64> @avx2_pslli_q_64(<4 x i64> %v) nounwind readnone uwtable {
+define <4 x i64> @avx2_pslli_q_64(<4 x i64> %v) {
; CHECK-LABEL: @avx2_pslli_q_64
; CHECK-NEXT: ret <4 x i64> zeroinitializer
%1 = tail call <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64> %v, i32 64)
@@ -373,14 +373,14 @@ define <4 x i64> @avx2_pslli_q_64(<4 x i
; ASHR - Constant Vector
;
-define <8 x i16> @sse2_psra_w_0(<8 x i16> %v) nounwind readnone uwtable {
+define <8 x i16> @sse2_psra_w_0(<8 x i16> %v) {
; CHECK-LABEL: @sse2_psra_w_0
; CHECK-NEXT: ret <8 x i16> %v
%1 = tail call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %v, <8 x i16> zeroinitializer)
ret <8 x i16> %1
}
-define <8 x i16> @sse2_psra_w_15(<8 x i16> %v) nounwind readnone uwtable {
+define <8 x i16> @sse2_psra_w_15(<8 x i16> %v) {
; CHECK-LABEL: @sse2_psra_w_15
; CHECK-NEXT: %1 = ashr <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
; CHECK-NEXT: ret <8 x i16> %1
@@ -388,7 +388,7 @@ define <8 x i16> @sse2_psra_w_15(<8 x i1
ret <8 x i16> %1
}
-define <8 x i16> @sse2_psra_w_15_splat(<8 x i16> %v) nounwind readnone uwtable {
+define <8 x i16> @sse2_psra_w_15_splat(<8 x i16> %v) {
; CHECK-LABEL: @sse2_psra_w_15_splat
; CHECK-NEXT: %1 = ashr <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
; CHECK-NEXT: ret <8 x i16> %1
@@ -396,7 +396,7 @@ define <8 x i16> @sse2_psra_w_15_splat(<
ret <8 x i16> %1
}
-define <8 x i16> @sse2_psra_w_64(<8 x i16> %v) nounwind readnone uwtable {
+define <8 x i16> @sse2_psra_w_64(<8 x i16> %v) {
; CHECK-LABEL: @sse2_psra_w_64
; CHECK-NEXT: %1 = ashr <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
; CHECK-NEXT: ret <8 x i16> %1
@@ -404,14 +404,14 @@ define <8 x i16> @sse2_psra_w_64(<8 x i1
ret <8 x i16> %1
}
-define <4 x i32> @sse2_psra_d_0(<4 x i32> %v) nounwind readnone uwtable {
+define <4 x i32> @sse2_psra_d_0(<4 x i32> %v) {
; CHECK-LABEL: @sse2_psra_d_0
; CHECK-NEXT: ret <4 x i32> %v
%1 = tail call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %v, <4 x i32> zeroinitializer)
ret <4 x i32> %1
}
-define <4 x i32> @sse2_psra_d_15(<4 x i32> %v) nounwind readnone uwtable {
+define <4 x i32> @sse2_psra_d_15(<4 x i32> %v) {
; CHECK-LABEL: @sse2_psra_d_15
; CHECK-NEXT: %1 = ashr <4 x i32> %v, <i32 15, i32 15, i32 15, i32 15>
; CHECK-NEXT: ret <4 x i32> %1
@@ -419,7 +419,7 @@ define <4 x i32> @sse2_psra_d_15(<4 x i3
ret <4 x i32> %1
}
-define <4 x i32> @sse2_psra_d_15_splat(<4 x i32> %v) nounwind readnone uwtable {
+define <4 x i32> @sse2_psra_d_15_splat(<4 x i32> %v) {
; CHECK-LABEL: @sse2_psra_d_15_splat
; CHECK-NEXT: %1 = ashr <4 x i32> %v, <i32 31, i32 31, i32 31, i32 31>
; CHECK-NEXT: ret <4 x i32> %1
@@ -427,7 +427,7 @@ define <4 x i32> @sse2_psra_d_15_splat(<
ret <4 x i32> %1
}
-define <4 x i32> @sse2_psra_d_64(<4 x i32> %v) nounwind readnone uwtable {
+define <4 x i32> @sse2_psra_d_64(<4 x i32> %v) {
; CHECK-LABEL: @sse2_psra_d_64
; CHECK-NEXT: %1 = ashr <4 x i32> %v, <i32 31, i32 31, i32 31, i32 31>
; CHECK-NEXT: ret <4 x i32> %1
@@ -435,14 +435,14 @@ define <4 x i32> @sse2_psra_d_64(<4 x i3
ret <4 x i32> %1
}
-define <16 x i16> @avx2_psra_w_0(<16 x i16> %v) nounwind readnone uwtable {
+define <16 x i16> @avx2_psra_w_0(<16 x i16> %v) {
; CHECK-LABEL: @avx2_psra_w_0
; CHECK-NEXT: ret <16 x i16> %v
%1 = tail call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> %v, <8 x i16> zeroinitializer)
ret <16 x i16> %1
}
-define <16 x i16> @avx2_psra_w_15(<16 x i16> %v) nounwind readnone uwtable {
+define <16 x i16> @avx2_psra_w_15(<16 x i16> %v) {
; CHECK-LABEL: @avx2_psra_w_15
; CHECK-NEXT: %1 = ashr <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
; CHECK-NEXT: ret <16 x i16> %1
@@ -450,7 +450,7 @@ define <16 x i16> @avx2_psra_w_15(<16 x
ret <16 x i16> %1
}
-define <16 x i16> @avx2_psra_w_15_splat(<16 x i16> %v) nounwind readnone uwtable {
+define <16 x i16> @avx2_psra_w_15_splat(<16 x i16> %v) {
; CHECK-LABEL: @avx2_psra_w_15_splat
; CHECK-NEXT: %1 = ashr <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
; CHECK-NEXT: ret <16 x i16> %1
@@ -458,7 +458,7 @@ define <16 x i16> @avx2_psra_w_15_splat(
ret <16 x i16> %1
}
-define <16 x i16> @avx2_psra_w_64(<16 x i16> %v) nounwind readnone uwtable {
+define <16 x i16> @avx2_psra_w_64(<16 x i16> %v) {
; CHECK-LABEL: @avx2_psra_w_64
; CHECK-NEXT: %1 = ashr <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
; CHECK-NEXT: ret <16 x i16> %1
@@ -466,14 +466,14 @@ define <16 x i16> @avx2_psra_w_64(<16 x
ret <16 x i16> %1
}
-define <8 x i32> @avx2_psra_d_0(<8 x i32> %v) nounwind readnone uwtable {
+define <8 x i32> @avx2_psra_d_0(<8 x i32> %v) {
; CHECK-LABEL: @avx2_psra_d_0
; CHECK-NEXT: ret <8 x i32> %v
%1 = tail call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> %v, <4 x i32> zeroinitializer)
ret <8 x i32> %1
}
-define <8 x i32> @avx2_psra_d_15(<8 x i32> %v) nounwind readnone uwtable {
+define <8 x i32> @avx2_psra_d_15(<8 x i32> %v) {
; CHECK-LABEL: @avx2_psra_d_15
; CHECK-NEXT: %1 = ashr <8 x i32> %v, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
; CHECK-NEXT: ret <8 x i32> %1
@@ -481,7 +481,7 @@ define <8 x i32> @avx2_psra_d_15(<8 x i3
ret <8 x i32> %1
}
-define <8 x i32> @avx2_psra_d_15_splat(<8 x i32> %v) nounwind readnone uwtable {
+define <8 x i32> @avx2_psra_d_15_splat(<8 x i32> %v) {
; CHECK-LABEL: @avx2_psra_d_15_splat
; CHECK-NEXT: %1 = ashr <8 x i32> %v, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
; CHECK-NEXT: ret <8 x i32> %1
@@ -489,7 +489,7 @@ define <8 x i32> @avx2_psra_d_15_splat(<
ret <8 x i32> %1
}
-define <8 x i32> @avx2_psra_d_64(<8 x i32> %v) nounwind readnone uwtable {
+define <8 x i32> @avx2_psra_d_64(<8 x i32> %v) {
; CHECK-LABEL: @avx2_psra_d_64
; CHECK-NEXT: %1 = ashr <8 x i32> %v, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
; CHECK-NEXT: ret <8 x i32> %1
@@ -501,14 +501,14 @@ define <8 x i32> @avx2_psra_d_64(<8 x i3
; LSHR - Constant Vector
;
-define <8 x i16> @sse2_psrl_w_0(<8 x i16> %v) nounwind readnone uwtable {
+define <8 x i16> @sse2_psrl_w_0(<8 x i16> %v) {
; CHECK-LABEL: @sse2_psrl_w_0
; CHECK-NEXT: ret <8 x i16> %v
%1 = tail call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %v, <8 x i16> zeroinitializer)
ret <8 x i16> %1
}
-define <8 x i16> @sse2_psrl_w_15(<8 x i16> %v) nounwind readnone uwtable {
+define <8 x i16> @sse2_psrl_w_15(<8 x i16> %v) {
; CHECK-LABEL: @sse2_psrl_w_15
; CHECK-NEXT: %1 = lshr <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
; CHECK-NEXT: ret <8 x i16> %1
@@ -516,28 +516,28 @@ define <8 x i16> @sse2_psrl_w_15(<8 x i1
ret <8 x i16> %1
}
-define <8 x i16> @sse2_psrl_w_15_splat(<8 x i16> %v) nounwind readnone uwtable {
+define <8 x i16> @sse2_psrl_w_15_splat(<8 x i16> %v) {
; CHECK-LABEL: @sse2_psrl_w_15_splat
; CHECK-NEXT: ret <8 x i16> zeroinitializer
%1 = tail call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %v, <8 x i16> <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>)
ret <8 x i16> %1
}
-define <8 x i16> @sse2_psrl_w_64(<8 x i16> %v) nounwind readnone uwtable {
+define <8 x i16> @sse2_psrl_w_64(<8 x i16> %v) {
; CHECK-LABEL: @sse2_psrl_w_64
; CHECK-NEXT: ret <8 x i16> zeroinitializer
%1 = tail call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %v, <8 x i16> <i16 64, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)
ret <8 x i16> %1
}
-define <4 x i32> @sse2_psrl_d_0(<4 x i32> %v) nounwind readnone uwtable {
+define <4 x i32> @sse2_psrl_d_0(<4 x i32> %v) {
; CHECK-LABEL: @sse2_psrl_d_0
; CHECK-NEXT: ret <4 x i32> %v
%1 = tail call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %v, <4 x i32> zeroinitializer)
ret <4 x i32> %1
}
-define <4 x i32> @sse2_psrl_d_15(<4 x i32> %v) nounwind readnone uwtable {
+define <4 x i32> @sse2_psrl_d_15(<4 x i32> %v) {
; CHECK-LABEL: @sse2_psrl_d_15
; CHECK-NEXT: %1 = lshr <4 x i32> %v, <i32 15, i32 15, i32 15, i32 15>
; CHECK-NEXT: ret <4 x i32> %1
@@ -545,28 +545,28 @@ define <4 x i32> @sse2_psrl_d_15(<4 x i3
ret <4 x i32> %1
}
-define <4 x i32> @sse2_psrl_d_15_splat(<4 x i32> %v) nounwind readnone uwtable {
+define <4 x i32> @sse2_psrl_d_15_splat(<4 x i32> %v) {
; CHECK-LABEL: @sse2_psrl_d_15_splat
; CHECK-NEXT: ret <4 x i32> zeroinitializer
%1 = tail call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %v, <4 x i32> <i32 15, i32 15, i32 15, i32 15>)
ret <4 x i32> %1
}
-define <4 x i32> @sse2_psrl_d_64(<4 x i32> %v) nounwind readnone uwtable {
+define <4 x i32> @sse2_psrl_d_64(<4 x i32> %v) {
; CHECK-LABEL: @sse2_psrl_d_64
; CHECK-NEXT: ret <4 x i32> zeroinitializer
%1 = tail call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %v, <4 x i32> <i32 64, i32 0, i32 9999, i32 9999>)
ret <4 x i32> %1
}
-define <2 x i64> @sse2_psrl_q_0(<2 x i64> %v) nounwind readnone uwtable {
+define <2 x i64> @sse2_psrl_q_0(<2 x i64> %v) {
; CHECK-LABEL: @sse2_psrl_q_0
; CHECK-NEXT: ret <2 x i64> %v
%1 = tail call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %v, <2 x i64> zeroinitializer)
ret <2 x i64> %1
}
-define <2 x i64> @sse2_psrl_q_15(<2 x i64> %v) nounwind readnone uwtable {
+define <2 x i64> @sse2_psrl_q_15(<2 x i64> %v) {
; CHECK-LABEL: @sse2_psrl_q_15
; CHECK-NEXT: %1 = lshr <2 x i64> %v, <i64 15, i64 15>
; CHECK-NEXT: ret <2 x i64> %1
@@ -574,21 +574,21 @@ define <2 x i64> @sse2_psrl_q_15(<2 x i6
ret <2 x i64> %1
}
-define <2 x i64> @sse2_psrl_q_64(<2 x i64> %v) nounwind readnone uwtable {
+define <2 x i64> @sse2_psrl_q_64(<2 x i64> %v) {
; CHECK-LABEL: @sse2_psrl_q_64
; CHECK-NEXT: ret <2 x i64> zeroinitializer
%1 = tail call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %v, <2 x i64> <i64 64, i64 9999>)
ret <2 x i64> %1
}
-define <16 x i16> @avx2_psrl_w_0(<16 x i16> %v) nounwind readnone uwtable {
+define <16 x i16> @avx2_psrl_w_0(<16 x i16> %v) {
; CHECK-LABEL: @avx2_psrl_w_0
; CHECK-NEXT: ret <16 x i16> %v
%1 = tail call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> %v, <8 x i16> zeroinitializer)
ret <16 x i16> %1
}
-define <16 x i16> @avx2_psrl_w_15(<16 x i16> %v) nounwind readnone uwtable {
+define <16 x i16> @avx2_psrl_w_15(<16 x i16> %v) {
; CHECK-LABEL: @avx2_psrl_w_15
; CHECK-NEXT: %1 = lshr <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
; CHECK-NEXT: ret <16 x i16> %1
@@ -596,28 +596,28 @@ define <16 x i16> @avx2_psrl_w_15(<16 x
ret <16 x i16> %1
}
-define <16 x i16> @avx2_psrl_w_15_splat(<16 x i16> %v) nounwind readnone uwtable {
+define <16 x i16> @avx2_psrl_w_15_splat(<16 x i16> %v) {
; CHECK-LABEL: @avx2_psrl_w_15_splat
; CHECK-NEXT: ret <16 x i16> zeroinitializer
%1 = tail call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> %v, <8 x i16> <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>)
ret <16 x i16> %1
}
-define <16 x i16> @avx2_psrl_w_64(<16 x i16> %v) nounwind readnone uwtable {
+define <16 x i16> @avx2_psrl_w_64(<16 x i16> %v) {
; CHECK-LABEL: @avx2_psrl_w_64
; CHECK-NEXT: ret <16 x i16> zeroinitializer
%1 = tail call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> %v, <8 x i16> <i16 64, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)
ret <16 x i16> %1
}
-define <8 x i32> @avx2_psrl_d_0(<8 x i32> %v) nounwind readnone uwtable {
+define <8 x i32> @avx2_psrl_d_0(<8 x i32> %v) {
; CHECK-LABEL: @avx2_psrl_d_0
; CHECK-NEXT: ret <8 x i32> %v
%1 = tail call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %v, <4 x i32> zeroinitializer)
ret <8 x i32> %1
}
-define <8 x i32> @avx2_psrl_d_15(<8 x i32> %v) nounwind readnone uwtable {
+define <8 x i32> @avx2_psrl_d_15(<8 x i32> %v) {
; CHECK-LABEL: @avx2_psrl_d_15
; CHECK-NEXT: %1 = lshr <8 x i32> %v, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
; CHECK-NEXT: ret <8 x i32> %1
@@ -625,28 +625,28 @@ define <8 x i32> @avx2_psrl_d_15(<8 x i3
ret <8 x i32> %1
}
-define <8 x i32> @avx2_psrl_d_15_splat(<8 x i32> %v) nounwind readnone uwtable {
+define <8 x i32> @avx2_psrl_d_15_splat(<8 x i32> %v) {
; CHECK-LABEL: @avx2_psrl_d_15_splat
; CHECK-NEXT: ret <8 x i32> zeroinitializer
%1 = tail call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %v, <4 x i32> <i32 15, i32 15, i32 15, i32 15>)
ret <8 x i32> %1
}
-define <8 x i32> @avx2_psrl_d_64(<8 x i32> %v) nounwind readnone uwtable {
+define <8 x i32> @avx2_psrl_d_64(<8 x i32> %v) {
; CHECK-LABEL: @avx2_psrl_d_64
; CHECK-NEXT: ret <8 x i32> zeroinitializer
%1 = tail call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %v, <4 x i32> <i32 64, i32 0, i32 9999, i32 9999>)
ret <8 x i32> %1
}
-define <4 x i64> @avx2_psrl_q_0(<4 x i64> %v) nounwind readnone uwtable {
+define <4 x i64> @avx2_psrl_q_0(<4 x i64> %v) {
; CHECK-LABEL: @avx2_psrl_q_0
; CHECK-NEXT: ret <4 x i64> %v
%1 = tail call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> %v, <2 x i64> zeroinitializer)
ret <4 x i64> %1
}
-define <4 x i64> @avx2_psrl_q_15(<4 x i64> %v) nounwind readnone uwtable {
+define <4 x i64> @avx2_psrl_q_15(<4 x i64> %v) {
; CHECK-LABEL: @avx2_psrl_q_15
; CHECK-NEXT: %1 = lshr <4 x i64> %v, <i64 15, i64 15, i64 15, i64 15>
; CHECK-NEXT: ret <4 x i64> %1
@@ -654,7 +654,7 @@ define <4 x i64> @avx2_psrl_q_15(<4 x i6
ret <4 x i64> %1
}
-define <4 x i64> @avx2_psrl_q_64(<4 x i64> %v) nounwind readnone uwtable {
+define <4 x i64> @avx2_psrl_q_64(<4 x i64> %v) {
; CHECK-LABEL: @avx2_psrl_q_64
; CHECK-NEXT: ret <4 x i64> zeroinitializer
%1 = tail call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> %v, <2 x i64> <i64 64, i64 9999>)
@@ -665,14 +665,14 @@ define <4 x i64> @avx2_psrl_q_64(<4 x i6
; SHL - Constant Vector
;
-define <8 x i16> @sse2_psll_w_0(<8 x i16> %v) nounwind readnone uwtable {
+define <8 x i16> @sse2_psll_w_0(<8 x i16> %v) {
; CHECK-LABEL: @sse2_psll_w_0
; CHECK-NEXT: ret <8 x i16> %v
%1 = tail call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> %v, <8 x i16> zeroinitializer)
ret <8 x i16> %1
}
-define <8 x i16> @sse2_psll_w_15(<8 x i16> %v) nounwind readnone uwtable {
+define <8 x i16> @sse2_psll_w_15(<8 x i16> %v) {
; CHECK-LABEL: @sse2_psll_w_15
; CHECK-NEXT: %1 = shl <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
; CHECK-NEXT: ret <8 x i16> %1
@@ -680,28 +680,28 @@ define <8 x i16> @sse2_psll_w_15(<8 x i1
ret <8 x i16> %1
}
-define <8 x i16> @sse2_psll_w_15_splat(<8 x i16> %v) nounwind readnone uwtable {
+define <8 x i16> @sse2_psll_w_15_splat(<8 x i16> %v) {
; CHECK-LABEL: @sse2_psll_w_15_splat
; CHECK-NEXT: ret <8 x i16> zeroinitializer
%1 = tail call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> %v, <8 x i16> <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>)
ret <8 x i16> %1
}
-define <8 x i16> @sse2_psll_w_64(<8 x i16> %v) nounwind readnone uwtable {
+define <8 x i16> @sse2_psll_w_64(<8 x i16> %v) {
; CHECK-LABEL: @sse2_psll_w_64
; CHECK-NEXT: ret <8 x i16> zeroinitializer
%1 = tail call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> %v, <8 x i16> <i16 64, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)
ret <8 x i16> %1
}
-define <4 x i32> @sse2_psll_d_0(<4 x i32> %v) nounwind readnone uwtable {
+define <4 x i32> @sse2_psll_d_0(<4 x i32> %v) {
; CHECK-LABEL: @sse2_psll_d_0
; CHECK-NEXT: ret <4 x i32> %v
%1 = tail call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %v, <4 x i32> zeroinitializer)
ret <4 x i32> %1
}
-define <4 x i32> @sse2_psll_d_15(<4 x i32> %v) nounwind readnone uwtable {
+define <4 x i32> @sse2_psll_d_15(<4 x i32> %v) {
; CHECK-LABEL: @sse2_psll_d_15
; CHECK-NEXT: %1 = shl <4 x i32> %v, <i32 15, i32 15, i32 15, i32 15>
; CHECK-NEXT: ret <4 x i32> %1
@@ -709,28 +709,28 @@ define <4 x i32> @sse2_psll_d_15(<4 x i3
ret <4 x i32> %1
}
-define <4 x i32> @sse2_psll_d_15_splat(<4 x i32> %v) nounwind readnone uwtable {
+define <4 x i32> @sse2_psll_d_15_splat(<4 x i32> %v) {
; CHECK-LABEL: @sse2_psll_d_15_splat
; CHECK-NEXT: ret <4 x i32> zeroinitializer
%1 = tail call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %v, <4 x i32> <i32 15, i32 15, i32 15, i32 15>)
ret <4 x i32> %1
}
-define <4 x i32> @sse2_psll_d_64(<4 x i32> %v) nounwind readnone uwtable {
+define <4 x i32> @sse2_psll_d_64(<4 x i32> %v) {
; CHECK-LABEL: @sse2_psll_d_64
; CHECK-NEXT: ret <4 x i32> zeroinitializer
%1 = tail call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %v, <4 x i32> <i32 64, i32 0, i32 9999, i32 9999>)
ret <4 x i32> %1
}
-define <2 x i64> @sse2_psll_q_0(<2 x i64> %v) nounwind readnone uwtable {
+define <2 x i64> @sse2_psll_q_0(<2 x i64> %v) {
; CHECK-LABEL: @sse2_psll_q_0
; CHECK-NEXT: ret <2 x i64> %v
%1 = tail call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %v, <2 x i64> zeroinitializer)
ret <2 x i64> %1
}
-define <2 x i64> @sse2_psll_q_15(<2 x i64> %v) nounwind readnone uwtable {
+define <2 x i64> @sse2_psll_q_15(<2 x i64> %v) {
; CHECK-LABEL: @sse2_psll_q_15
; CHECK-NEXT: %1 = shl <2 x i64> %v, <i64 15, i64 15>
; CHECK-NEXT: ret <2 x i64> %1
@@ -738,21 +738,21 @@ define <2 x i64> @sse2_psll_q_15(<2 x i6
ret <2 x i64> %1
}
-define <2 x i64> @sse2_psll_q_64(<2 x i64> %v) nounwind readnone uwtable {
+define <2 x i64> @sse2_psll_q_64(<2 x i64> %v) {
; CHECK-LABEL: @sse2_psll_q_64
; CHECK-NEXT: ret <2 x i64> zeroinitializer
%1 = tail call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %v, <2 x i64> <i64 64, i64 9999>)
ret <2 x i64> %1
}
-define <16 x i16> @avx2_psll_w_0(<16 x i16> %v) nounwind readnone uwtable {
+define <16 x i16> @avx2_psll_w_0(<16 x i16> %v) {
; CHECK-LABEL: @avx2_psll_w_0
; CHECK-NEXT: ret <16 x i16> %v
%1 = tail call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> %v, <8 x i16> zeroinitializer)
ret <16 x i16> %1
}
-define <16 x i16> @avx2_psll_w_15(<16 x i16> %v) nounwind readnone uwtable {
+define <16 x i16> @avx2_psll_w_15(<16 x i16> %v) {
; CHECK-LABEL: @avx2_psll_w_15
; CHECK-NEXT: %1 = shl <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
; CHECK-NEXT: ret <16 x i16> %1
@@ -760,28 +760,28 @@ define <16 x i16> @avx2_psll_w_15(<16 x
ret <16 x i16> %1
}
-define <16 x i16> @avx2_psll_w_15_splat(<16 x i16> %v) nounwind readnone uwtable {
+define <16 x i16> @avx2_psll_w_15_splat(<16 x i16> %v) {
; CHECK-LABEL: @avx2_psll_w_15_splat
; CHECK-NEXT: ret <16 x i16> zeroinitializer
%1 = tail call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> %v, <8 x i16> <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>)
ret <16 x i16> %1
}
-define <16 x i16> @avx2_psll_w_64(<16 x i16> %v) nounwind readnone uwtable {
+define <16 x i16> @avx2_psll_w_64(<16 x i16> %v) {
; CHECK-LABEL: @avx2_psll_w_64
; CHECK-NEXT: ret <16 x i16> zeroinitializer
%1 = tail call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> %v, <8 x i16> <i16 64, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)
ret <16 x i16> %1
}
-define <8 x i32> @avx2_psll_d_0(<8 x i32> %v) nounwind readnone uwtable {
+define <8 x i32> @avx2_psll_d_0(<8 x i32> %v) {
; CHECK-LABEL: @avx2_psll_d_0
; CHECK-NEXT: ret <8 x i32> %v
%1 = tail call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %v, <4 x i32> zeroinitializer)
ret <8 x i32> %1
}
-define <8 x i32> @avx2_psll_d_15(<8 x i32> %v) nounwind readnone uwtable {
+define <8 x i32> @avx2_psll_d_15(<8 x i32> %v) {
; CHECK-LABEL: @avx2_psll_d_15
; CHECK-NEXT: %1 = shl <8 x i32> %v, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
; CHECK-NEXT: ret <8 x i32> %1
@@ -789,28 +789,28 @@ define <8 x i32> @avx2_psll_d_15(<8 x i3
ret <8 x i32> %1
}
-define <8 x i32> @avx2_psll_d_15_splat(<8 x i32> %v) nounwind readnone uwtable {
+define <8 x i32> @avx2_psll_d_15_splat(<8 x i32> %v) {
; CHECK-LABEL: @avx2_psll_d_15_splat
; CHECK-NEXT: ret <8 x i32> zeroinitializer
%1 = tail call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %v, <4 x i32> <i32 15, i32 15, i32 15, i32 15>)
ret <8 x i32> %1
}
-define <8 x i32> @avx2_psll_d_64(<8 x i32> %v) nounwind readnone uwtable {
+define <8 x i32> @avx2_psll_d_64(<8 x i32> %v) {
; CHECK-LABEL: @avx2_psll_d_64
; CHECK-NEXT: ret <8 x i32> zeroinitializer
%1 = tail call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %v, <4 x i32> <i32 64, i32 0, i32 9999, i32 9999>)
ret <8 x i32> %1
}
-define <4 x i64> @avx2_psll_q_0(<4 x i64> %v) nounwind readnone uwtable {
+define <4 x i64> @avx2_psll_q_0(<4 x i64> %v) {
; CHECK-LABEL: @avx2_psll_q_0
; CHECK-NEXT: ret <4 x i64> %v
%1 = tail call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> %v, <2 x i64> zeroinitializer)
ret <4 x i64> %1
}
-define <4 x i64> @avx2_psll_q_15(<4 x i64> %v) nounwind readnone uwtable {
+define <4 x i64> @avx2_psll_q_15(<4 x i64> %v) {
; CHECK-LABEL: @avx2_psll_q_15
; CHECK-NEXT: %1 = shl <4 x i64> %v, <i64 15, i64 15, i64 15, i64 15>
; CHECK-NEXT: ret <4 x i64> %1
@@ -818,7 +818,7 @@ define <4 x i64> @avx2_psll_q_15(<4 x i6
ret <4 x i64> %1
}
-define <4 x i64> @avx2_psll_q_64(<4 x i64> %v) nounwind readnone uwtable {
+define <4 x i64> @avx2_psll_q_64(<4 x i64> %v) {
; CHECK-LABEL: @avx2_psll_q_64
; CHECK-NEXT: ret <4 x i64> zeroinitializer
%1 = tail call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> %v, <2 x i64> <i64 64, i64 9999>)
@@ -829,7 +829,7 @@ define <4 x i64> @avx2_psll_q_64(<4 x i6
; Vector Demanded Bits
;
-define <8 x i16> @sse2_psra_w_var(<8 x i16> %v, <8 x i16> %a) nounwind readnone uwtable {
+define <8 x i16> @sse2_psra_w_var(<8 x i16> %v, <8 x i16> %a) {
; CHECK-LABEL: @sse2_psra_w_var
; CHECK-NEXT: %1 = tail call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %v, <8 x i16> %a)
; CHECK-NEXT: ret <8 x i16> %1
@@ -838,7 +838,7 @@ define <8 x i16> @sse2_psra_w_var(<8 x i
ret <8 x i16> %2
}
-define <4 x i32> @sse2_psra_d_var(<4 x i32> %v, <4 x i32> %a) nounwind readnone uwtable {
+define <4 x i32> @sse2_psra_d_var(<4 x i32> %v, <4 x i32> %a) {
; CHECK-LABEL: @sse2_psra_d_var
; CHECK-NEXT: %1 = tail call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %v, <4 x i32> %a)
; CHECK-NEXT: ret <4 x i32> %1
@@ -847,7 +847,7 @@ define <4 x i32> @sse2_psra_d_var(<4 x i
ret <4 x i32> %2
}
-define <16 x i16> @avx2_psra_w_var(<16 x i16> %v, <8 x i16> %a) nounwind readnone uwtable {
+define <16 x i16> @avx2_psra_w_var(<16 x i16> %v, <8 x i16> %a) {
; CHECK-LABEL: @avx2_psra_w_var
; CHECK-NEXT: %1 = tail call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> %v, <8 x i16> %a)
; CHECK-NEXT: ret <16 x i16> %1
@@ -856,7 +856,7 @@ define <16 x i16> @avx2_psra_w_var(<16 x
ret <16 x i16> %2
}
-define <8 x i32> @avx2_psra_d_var(<8 x i32> %v, <4 x i32> %a) nounwind readnone uwtable {
+define <8 x i32> @avx2_psra_d_var(<8 x i32> %v, <4 x i32> %a) {
; CHECK-LABEL: @avx2_psra_d_var
; CHECK-NEXT: %1 = tail call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> %v, <4 x i32> %a)
; CHECK-NEXT: ret <8 x i32> %1
@@ -865,7 +865,7 @@ define <8 x i32> @avx2_psra_d_var(<8 x i
ret <8 x i32> %2
}
-define <8 x i16> @sse2_psrl_w_var(<8 x i16> %v, <8 x i16> %a) nounwind readnone uwtable {
+define <8 x i16> @sse2_psrl_w_var(<8 x i16> %v, <8 x i16> %a) {
; CHECK-LABEL: @sse2_psrl_w_var
; CHECK-NEXT: %1 = tail call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %v, <8 x i16> %a)
; CHECK-NEXT: ret <8 x i16> %1
@@ -874,7 +874,7 @@ define <8 x i16> @sse2_psrl_w_var(<8 x i
ret <8 x i16> %2
}
-define <4 x i32> @sse2_psrl_d_var(<4 x i32> %v, <4 x i32> %a) nounwind readnone uwtable {
+define <4 x i32> @sse2_psrl_d_var(<4 x i32> %v, <4 x i32> %a) {
; CHECK-LABEL: @sse2_psrl_d_var
; CHECK-NEXT: %1 = tail call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %v, <4 x i32> %a)
; CHECK-NEXT: ret <4 x i32> %1
@@ -883,7 +883,7 @@ define <4 x i32> @sse2_psrl_d_var(<4 x i
ret <4 x i32> %2
}
-define <2 x i64> @sse2_psrl_q_var(<2 x i64> %v, <2 x i64> %a) nounwind readnone uwtable {
+define <2 x i64> @sse2_psrl_q_var(<2 x i64> %v, <2 x i64> %a) {
; CHECK-LABEL: @sse2_psrl_q_var
; CHECK-NEXT: %1 = tail call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %v, <2 x i64> %a)
; CHECK-NEXT: ret <2 x i64> %1
@@ -892,7 +892,7 @@ define <2 x i64> @sse2_psrl_q_var(<2 x i
ret <2 x i64> %2
}
-define <16 x i16> @avx2_psrl_w_var(<16 x i16> %v, <8 x i16> %a) nounwind readnone uwtable {
+define <16 x i16> @avx2_psrl_w_var(<16 x i16> %v, <8 x i16> %a) {
; CHECK-LABEL: @avx2_psrl_w_var
; CHECK-NEXT: %1 = tail call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> %v, <8 x i16> %a)
; CHECK-NEXT: ret <16 x i16> %1
@@ -901,7 +901,7 @@ define <16 x i16> @avx2_psrl_w_var(<16 x
ret <16 x i16> %2
}
-define <8 x i32> @avx2_psrl_d_var(<8 x i32> %v, <4 x i32> %a) nounwind readnone uwtable {
+define <8 x i32> @avx2_psrl_d_var(<8 x i32> %v, <4 x i32> %a) {
; CHECK-LABEL: @avx2_psrl_d_var
; CHECK-NEXT: %1 = tail call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %v, <4 x i32> %a)
; CHECK-NEXT: ret <8 x i32> %1
@@ -910,7 +910,7 @@ define <8 x i32> @avx2_psrl_d_var(<8 x i
ret <8 x i32> %2
}
-define <4 x i64> @avx2_psrl_q_var(<4 x i64> %v, <2 x i64> %a) nounwind readnone uwtable {
+define <4 x i64> @avx2_psrl_q_var(<4 x i64> %v, <2 x i64> %a) {
; CHECK-LABEL: @avx2_psrl_q_var
; CHECK-NEXT: %1 = tail call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> %v, <2 x i64> %a)
; CHECK-NEXT: ret <4 x i64> %1
@@ -919,7 +919,7 @@ define <4 x i64> @avx2_psrl_q_var(<4 x i
ret <4 x i64> %2
}
-define <8 x i16> @sse2_psll_w_var(<8 x i16> %v, <8 x i16> %a) nounwind readnone uwtable {
+define <8 x i16> @sse2_psll_w_var(<8 x i16> %v, <8 x i16> %a) {
; CHECK-LABEL: @sse2_psll_w_var
; CHECK-NEXT: %1 = tail call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> %v, <8 x i16> %a)
; CHECK-NEXT: ret <8 x i16> %1
@@ -928,7 +928,7 @@ define <8 x i16> @sse2_psll_w_var(<8 x i
ret <8 x i16> %2
}
-define <4 x i32> @sse2_psll_d_var(<4 x i32> %v, <4 x i32> %a) nounwind readnone uwtable {
+define <4 x i32> @sse2_psll_d_var(<4 x i32> %v, <4 x i32> %a) {
; CHECK-LABEL: @sse2_psll_d_var
; CHECK-NEXT: %1 = tail call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %v, <4 x i32> %a)
; CHECK-NEXT: ret <4 x i32> %1
@@ -937,7 +937,7 @@ define <4 x i32> @sse2_psll_d_var(<4 x i
ret <4 x i32> %2
}
-define <2 x i64> @sse2_psll_q_var(<2 x i64> %v, <2 x i64> %a) nounwind readnone uwtable {
+define <2 x i64> @sse2_psll_q_var(<2 x i64> %v, <2 x i64> %a) {
; CHECK-LABEL: @sse2_psll_q_var
; CHECK-NEXT: %1 = tail call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %v, <2 x i64> %a)
; CHECK-NEXT: ret <2 x i64> %1
@@ -946,7 +946,7 @@ define <2 x i64> @sse2_psll_q_var(<2 x i
ret <2 x i64> %2
}
-define <16 x i16> @avx2_psll_w_var(<16 x i16> %v, <8 x i16> %a) nounwind readnone uwtable {
+define <16 x i16> @avx2_psll_w_var(<16 x i16> %v, <8 x i16> %a) {
; CHECK-LABEL: @avx2_psll_w_var
; CHECK-NEXT: %1 = tail call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> %v, <8 x i16> %a)
; CHECK-NEXT: ret <16 x i16> %1
@@ -955,7 +955,7 @@ define <16 x i16> @avx2_psll_w_var(<16 x
ret <16 x i16> %2
}
-define <8 x i32> @avx2_psll_d_var(<8 x i32> %v, <4 x i32> %a) nounwind readnone uwtable {
+define <8 x i32> @avx2_psll_d_var(<8 x i32> %v, <4 x i32> %a) {
; CHECK-LABEL: @avx2_psll_d_var
; CHECK-NEXT: %1 = tail call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %v, <4 x i32> %a)
; CHECK-NEXT: ret <8 x i32> %1
@@ -964,7 +964,7 @@ define <8 x i32> @avx2_psll_d_var(<8 x i
ret <8 x i32> %2
}
-define <4 x i64> @avx2_psll_q_var(<4 x i64> %v, <2 x i64> %a) nounwind readnone uwtable {
+define <4 x i64> @avx2_psll_q_var(<4 x i64> %v, <2 x i64> %a) {
; CHECK-LABEL: @avx2_psll_q_var
; CHECK-NEXT: %1 = tail call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> %v, <2 x i64> %a)
; CHECK-NEXT: ret <4 x i64> %1
@@ -1053,7 +1053,7 @@ define <8 x i32> @test_avx2_psra_d_8() {
ret <8 x i32> %4
}
-define <2 x i64> @test_sse2_1() nounwind readnone uwtable {
+define <2 x i64> @test_sse2_1() {
%S = bitcast i32 1 to i32
%1 = zext i32 %S to i64
%2 = insertelement <2 x i64> undef, i64 %1, i32 0
@@ -1076,7 +1076,7 @@ define <2 x i64> @test_sse2_1() nounwind
; CHECK: ret <2 x i64> <i64 72058418680037440, i64 144117112246370624>
}
-define <4 x i64> @test_avx2_1() nounwind readnone uwtable {
+define <4 x i64> @test_avx2_1() {
%S = bitcast i32 1 to i32
%1 = zext i32 %S to i64
%2 = insertelement <2 x i64> undef, i64 %1, i32 0
@@ -1099,7 +1099,7 @@ define <4 x i64> @test_avx2_1() nounwind
; CHECK: ret <4 x i64> <i64 64, i64 128, i64 192, i64 256>
}
-define <2 x i64> @test_sse2_0() nounwind readnone uwtable {
+define <2 x i64> @test_sse2_0() {
%S = bitcast i32 128 to i32
%1 = zext i32 %S to i64
%2 = insertelement <2 x i64> undef, i64 %1, i32 0
@@ -1122,7 +1122,7 @@ define <2 x i64> @test_sse2_0() nounwind
; CHECK: ret <2 x i64> zeroinitializer
}
-define <4 x i64> @test_avx2_0() nounwind readnone uwtable {
+define <4 x i64> @test_avx2_0() {
%S = bitcast i32 128 to i32
%1 = zext i32 %S to i64
%2 = insertelement <2 x i64> undef, i64 %1, i32 0
@@ -1144,7 +1144,7 @@ define <4 x i64> @test_avx2_0() nounwind
; CHECK: test_avx2_0
; CHECK: ret <4 x i64> zeroinitializer
}
-define <2 x i64> @test_sse2_psrl_1() nounwind readnone uwtable {
+define <2 x i64> @test_sse2_psrl_1() {
%S = bitcast i32 1 to i32
%1 = zext i32 %S to i64
%2 = insertelement <2 x i64> undef, i64 %1, i32 0
@@ -1167,7 +1167,7 @@ define <2 x i64> @test_sse2_psrl_1() nou
; CHECK: ret <2 x i64> <i64 562954248421376, i64 9007267974742020>
}
-define <4 x i64> @test_avx2_psrl_1() nounwind readnone uwtable {
+define <4 x i64> @test_avx2_psrl_1() {
%S = bitcast i32 1 to i32
%1 = zext i32 %S to i64
%2 = insertelement <2 x i64> undef, i64 %1, i32 0
@@ -1190,7 +1190,7 @@ define <4 x i64> @test_avx2_psrl_1() nou
; CHECK: ret <4 x i64> <i64 16, i64 32, i64 64, i64 128>
}
-define <2 x i64> @test_sse2_psrl_0() nounwind readnone uwtable {
+define <2 x i64> @test_sse2_psrl_0() {
%S = bitcast i32 128 to i32
%1 = zext i32 %S to i64
%2 = insertelement <2 x i64> undef, i64 %1, i32 0
@@ -1213,7 +1213,7 @@ define <2 x i64> @test_sse2_psrl_0() nou
; CHECK: ret <2 x i64> zeroinitializer
}
-define <4 x i64> @test_avx2_psrl_0() nounwind readnone uwtable {
+define <4 x i64> @test_avx2_psrl_0() {
%S = bitcast i32 128 to i32
%1 = zext i32 %S to i64
%2 = insertelement <2 x i64> undef, i64 %1, i32 0
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