[llvm] r248657 - AMDGPU: Remove hasPostISelHook from most instructions
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 25 22:06:48 PDT 2015
Author: arsenm
Date: Sat Sep 26 00:06:48 2015
New Revision: 248657
URL: http://llvm.org/viewvc/llvm-project?rev=248657&view=rev
Log:
AMDGPU: Remove hasPostISelHook from most instructions
Since this is only needed for VOP3 and a few other special
case instructions, stop setting it on everything.
Modified:
llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td?rev=248657&r1=248656&r2=248657&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td Sat Sep 26 00:06:48 2015
@@ -69,9 +69,6 @@ class InstSI <dag outs, dag ins, string
let TSFlags{20} = WQM;
let TSFlags{21} = VGPRSpill;
- // Most instructions require adjustments after selection to satisfy
- // operand requirements.
- let hasPostISelHook = 1;
let SchedRW = [Write32Bit];
}
@@ -137,6 +134,11 @@ class VOP3Common <dag outs, dag ins, str
let isCodeGenOnly = 0;
int Size = 8;
+
+ // Because SGPRs may be allowed if there are multiple operands, we
+ // need a post-isel hook to insert copies in order to avoid
+ // violating constant bus requirements.
+ let hasPostISelHook = 1;
}
} // End Uses = [EXEC]
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td?rev=248657&r1=248656&r2=248657&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td Sat Sep 26 00:06:48 2015
@@ -2061,12 +2061,14 @@ multiclass DS_1A1D_RET <bits<8> op, stri
dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds),
string asm = opName#" $vdst, $addr, $data0"#"$offset$gds"> {
- def "" : DS_Pseudo <opName, outs, ins, []>,
- AtomicNoRet<noRetOp, 1>;
+ let hasPostISelHook = 1 in {
+ def "" : DS_Pseudo <opName, outs, ins, []>,
+ AtomicNoRet<noRetOp, 1>;
- let data1 = 0 in {
- def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
- def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
+ let data1 = 0 in {
+ def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
+ def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
+ }
}
}
@@ -2075,11 +2077,13 @@ multiclass DS_1A2D_RET_m <bits<8> op, st
dag outs = (outs rc:$vdst),
string asm = opName#" $vdst, $addr, $data0, $data1"#"$offset"#"$gds"> {
- def "" : DS_Pseudo <opName, outs, ins, []>,
- AtomicNoRet<noRetOp, 1>;
+ let hasPostISelHook = 1 in {
+ def "" : DS_Pseudo <opName, outs, ins, []>,
+ AtomicNoRet<noRetOp, 1>;
- def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
- def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
+ def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
+ def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
+ }
}
multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
@@ -2561,6 +2565,7 @@ multiclass FLAT_ATOMIC <bits<7> op, stri
name#" $vdst, $addr, $data glc"#"$slc"#"$tfe", []>,
AtomicNoRet <NAME, 1> {
let glc = 1;
+ let hasPostISelHook = 1;
}
}
}
More information about the llvm-commits
mailing list