[PATCH] D12635: merge vector stores into wider vector stores and fix AArch64 misaligned access TLI hook (PR21711)

Sanjay Patel via llvm-commits llvm-commits at lists.llvm.org
Fri Sep 25 14:09:16 PDT 2015

spatel added a comment.

Please see the discussion in http://reviews.llvm.org/D12154.

I don't think we take cacheline-crossing penalties into account anywhere in the compiler. Ie, we produce unaligned accesses for all x86 targets when we can merge smaller ops together to reduce the instruction count.

Note that we do have CPU attributes (eg, FeatureSlowUAMem32) that change this behavior; see unaligned-32-byte-memops.ll for examples of how that works.


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