[llvm] r248540 - [AArch64] Improve the readability of the ld/st optimization pass. NFC.

[Chad Rosier via llvm-commits]

Author: mcrosier
Date: Thu Sep 24 16:27:49 2015
New Revision: 248540

URL: http://llvm.org/viewvc/llvm-project?rev=248540&view=rev
Log:
[AArch64] Improve the readability of the ld/st optimization pass. NFC.

In this context, MI is an add/sub instruction not a loads/store.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

Modified: llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp?rev=248540&r1=248539&r2=248540&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp Thu Sep 24 16:27:49 2015
@@ -750,10 +750,10 @@ static bool isMatchingUpdateInsn(Machine
       break;
     // If the instruction has the base register as source and dest and the
     // immediate will fit in a signed 9-bit integer, then we have a match.
-    if (getLdStRegOp(MI).getReg() == BaseReg &&
-        getLdStBaseOp(MI).getReg() == BaseReg &&
-        getLdStOffsetOp(MI).getImm() <= 255 &&
-        getLdStOffsetOp(MI).getImm() >= -256) {
+    if (MI->getOperand(0).getReg() == BaseReg &&
+        MI->getOperand(1).getReg() == BaseReg &&
+        MI->getOperand(2).getImm() <= 255 &&
+        MI->getOperand(2).getImm() >= -256) {
       // If we have a non-zero Offset, we check that it matches the amount
       // we're adding to the register.
       if (!Offset || Offset == MI->getOperand(2).getImm())