[llvm] r248528 - [AArch64] The paired post-increment store instruction has an output register.

Chad Rosier via llvm-commits llvm-commits at lists.llvm.org
Thu Sep 24 12:21:42 PDT 2015

Author: mcrosier
Date: Thu Sep 24 14:21:42 2015
New Revision: 248528

URL: http://llvm.org/viewvc/llvm-project?rev=248528&view=rev
[AArch64] The paired post-increment store instruction has an output register.

The pre- and post-increment version update the base register, but the post-
version was defined incorrectly.  There is no test case as we don't currently
generate these instructions, but I plan on changing that in the near future.


Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td?rev=248528&r1=248527&r2=248528&view=diff
--- llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td Thu Sep 24 14:21:42 2015
@@ -3253,8 +3253,8 @@ class LoadPairPostIdx<bits<2> opc, bit V
 let mayStore = 1, mayLoad = 0 in
 class StorePairPostIdx<bits<2> opc, bit V, RegisterClass regtype,
                        Operand idxtype, string asm>
-    : BaseLoadStorePairPostIdx<opc, V, 0, (outs),
-                             (ins GPR64sp:$wback, regtype:$Rt, regtype:$Rt2,
+    : BaseLoadStorePairPostIdx<opc, V, 0, (outs GPR64sp:$wback),
+                             (ins regtype:$Rt, regtype:$Rt2,
                                   GPR64sp:$Rn, idxtype:$offset),
       Sched<[WriteAdr, WriteSTP]>;

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