[PATCH] D12193: [mips][p5600] Added P5600 processor and initial scheduler.
Matthew Fortune via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 24 06:19:15 PDT 2015
mpf added a subscriber: mpf.
Comment at: lib/Target/Mips/MipsScheduleP5600.td:16
@@ +15,3 @@
+ let CompleteModel = 1;
> dsanders wrote:
> > vkalintiris wrote:
> > > Shouldn't we set this to zero? This is my understanding (from the relevant comment in the definition of CompleteModel) given that we don't define itineraries for every instruction.
> > We should cover every instruction present in P5600 at this point. If I've missed any then that's a bug in the scheduler and it should be fixed. If CompleteModel is 1, we will assert on unexpected instructions but if it's 0 then we will silently assign some scheduling information.
> > If I've missed any then that's a bug in the scheduler and it should be fixed.
> Okay then that sounds fine.
I have some concerns about this as we are potentially making it impossible to use the P5600 scheduler (in a release version of LLVM) because someone happens to hit an instruction that did not get triggered in any testing of p5600. 99% of the scheduler would be OK in that environment with just a few corner cases of bad scheduling information.
Do other architectures set CompleteModel to '1'? If so then fine otherwise can you make a production/release build of the compiler just generate a warning if it hits a missing instruction (but continue) and have a debug compiler abort (or something along the same lines)? Just trying to make sure we don't end up with this scheduler being in place but unusable because of a corner case. Bearing in mind that if one file in an application can't build with the p5600 scheduler then many build systems will need to turn it off for all files.
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