[llvm] r248399 - [x86] move code for converting int logic to FP logic to a helper function; NFCI

[Sanjay Patel via llvm-commits]

Author: spatel
Date: Wed Sep 23 12:39:41 2015
New Revision: 248399

URL: http://llvm.org/viewvc/llvm-project?rev=248399&view=rev
Log:
[x86] move code for converting int logic to FP logic to a helper function; NFCI

This is a follow-on to:
http://reviews.llvm.org/rL248395

so we can add the call to the or/xor combines too.


Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=248399&r1=248398&r2=248399&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Sep 23 12:39:41 2015
@@ -24409,6 +24409,41 @@ static SDValue VectorZextCombine(SDNode
   return DAG.getBitcast(N0.getValueType(), NewShuffle);
 }
 
+/// If both input operands of a logic op are being cast from floating point
+/// types, try to convert this into a floating point logic node to avoid
+/// unnecessary moves from SSE to integer registers.
+static SDValue convertIntLogicToFPLogic(SDNode *N, SelectionDAG &DAG,
+                                        const X86Subtarget *Subtarget) {
+  unsigned FPOpcode = ISD::DELETED_NODE;
+  if (N->getOpcode() == ISD::AND)
+    FPOpcode = X86ISD::FAND;
+  else if (N->getOpcode() == ISD::OR)
+    FPOpcode = X86ISD::FOR;
+  else if (N->getOpcode() == ISD::XOR)
+    FPOpcode = X86ISD::FXOR;
+
+  assert(FPOpcode != ISD::DELETED_NODE &&
+         "Unexpected input node for FP logic conversion");
+
+  EVT VT = N->getValueType(0);
+  SDValue N0 = N->getOperand(0);
+  SDValue N1 = N->getOperand(1);
+  SDLoc DL(N);
+  if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
+      ((Subtarget->hasSSE1() && VT == MVT::i32) ||
+       (Subtarget->hasSSE2() && VT == MVT::i64))) {
+    SDValue N00 = N0.getOperand(0);
+    SDValue N10 = N1.getOperand(0);
+    EVT N00Type = N00.getValueType();
+    EVT N10Type = N10.getValueType();
+    if (N00Type.isFloatingPoint() && N10Type.isFloatingPoint()) {
+      SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
+      return DAG.getBitcast(VT, FPLogic);
+    }
+  }
+  return SDValue();
+}
+
 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
                                  TargetLowering::DAGCombinerInfo &DCI,
                                  const X86Subtarget *Subtarget) {
@@ -24447,23 +24482,8 @@ static SDValue PerformAndCombine(SDNode
       }
     } // BEXTR
 
-    // If both input operands are being cast from floating point types,
-    // try to convert this into a floating point logic node to avoid
-    // unnecessary moves from SSE to integer registers.
-    // FIXME: Split this into a helper function, so it can also be used with
-    //        or/xor combining.
-    if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
-        ((Subtarget->hasSSE1() && VT == MVT::i32) ||
-         (Subtarget->hasSSE2() && VT == MVT::i64))) {
-      SDValue N00 = N0.getOperand(0);
-      SDValue N10 = N1.getOperand(0);
-      EVT N00Type = N00.getValueType();
-      EVT N10Type = N10.getValueType();
-      if (N00Type.isFloatingPoint() && N10Type.isFloatingPoint()) {
-        SDValue FLogic = DAG.getNode(X86ISD::FAND, DL, N00Type, N00, N10);
-        return DAG.getBitcast(VT, FLogic);
-      }
-    }
+    if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
+      return FPLogic;
 
     return SDValue();
   }