[PATCH] D12742: [ARM] Scaling up values in ARMBaseInstrInfo::isProfitableToIfCvt() before they are scaled by a probability to avoid precision issue.

[Cong Hou via llvm-commits]

congh added a comment.

With further investigation, I found that pipeline stalls both occur w/ and w/o this patch. The stalls reported by LLVM are from waiting for vld being finished before using its loaded values. This is also true when two vld are put in two braches. LLVM  doesn't report any stall just because the use of the loaded values and vld are in different basic blocks and the scheduler (which print stalls) only considers instructions in the same block. Therefore, I think the if-converter doesn't have to take care of this case specially.


http://reviews.llvm.org/D12742