[PATCH] D12663: [X86][SSE] Vectorize CTTZ + CTTZ_ZERO_UNDEF

[Quentin Colombet via llvm-commits]

qcolombet added a comment.

Hi Simon,

> Originally I was intending to implement this generically in the VectorLegalizer but hit the issue that the 2i64 implementations were vectorized and saw a large perf regression.


Pushing that into generic code may make sense, we would need to be careful with the cost model though. I.e., AND and SUB may not be legal on the target.

Anyhow, LGTM.

Thanks,
-Quentin


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:17075
@@ +17074,3 @@
+    SDValue LSB = DAG.getNode(ISD::AND, dl, VT, N0,
+                              DAG.getNode(ISD::SUB, dl, VT, Zero, N0));
+
----------------
Wouldn’t hurt to write the pattern we build here: x & -x


Repository:
  rL LLVM

http://reviews.llvm.org/D12663