[PATCH] D11798: [mips][microMIPS] Implement BOVC, BNVC, EXT, INS, JALRC, PREFE and NAL instructions
Daniel Sanders via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 16 05:09:26 PDT 2015
dsanders added a comment.
Your commit message and patch don't agree with each other since there's no mention of BOVC, BNVC, and NAL in the patch. Is some of the patch missing?
================
Comment at: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp:801
@@ +800,3 @@
+ unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
+ STI) << 16;
+ unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
----------------
Indentation
================
Comment at: lib/Target/Mips/MicroMips32r6InstrFormats.td:21
@@ +20,3 @@
+ let PrintMethod = "printMemOperand";
+ let MIOperandInfo = (ops GPR32, simm12);
+ let EncoderMethod = "getMemEncodingMMImm9";
----------------
simm12 -> simm9
================
Comment at: lib/Target/Mips/MicroMips32r6InstrFormats.td:233-277
@@ -224,2 +232,47 @@
+class EXT_FM_MMR6<bits<6> funct> {
+ bits<5> rt;
+ bits<5> rs;
+ bits<5> size;
+ bits<5> pos;
+
+ bits<32> Inst;
+
+ let Inst{31-26} = 0;
+ let Inst{25-21} = rt;
+ let Inst{20-16} = rs;
+ let Inst{15-11} = size;
+ let Inst{10-6} = pos;
+ let Inst{5-0} = funct;
+}
+
+class PREFE_FM_MMR6<bits<6> op, bits<3> funct> : MipsR6Inst {
+ bits<21> addr;
+ bits<5> hint;
+ bits<5> base = addr{20-16};
+ bits<9> offset = addr{8-0};
+
+ bits<32> Inst;
+
+ let Inst{31-26} = op;
+ let Inst{25-21} = hint;
+ let Inst{20-16} = base;
+ let Inst{15-12} = 0b1010;
+ let Inst{11-9} = funct;
+ let Inst{8-0} = offset;
+}
+
+class JALRC_FM_MMR6 {
+ bits<5> rt;
+ bits<5> rs;
+
+ bits<32> Inst;
+
+ let Inst{31-26} = 0;
+ let Inst{25-21} = rt;
+ let Inst{20-16} = rs;
+ let Inst{15-6} = 0b0000111100;
+ let Inst{5-0} = 0b111100;
+}
+
class ERET_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm> {
----------------
Naming convention. These are missing the major opcode prefix:
EXT/INS => POOL32A
PREFE => POOL32C
JALRC => POOL32A
================
Comment at: lib/Target/Mips/MicroMips32r6InstrInfo.td:284-330
@@ -279,2 +283,49 @@
+class EXT_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO, Operand PosOpnd,
+ SDPatternOperator Op = null_frag> : MMR6Arch<instr_asm>,
+ MipsR6Inst {
+ dag OutOperandList = (outs RO:$rt);
+ dag InOperandList = (ins RO:$rs, PosOpnd:$pos, size_ext:$size);
+ string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $pos, $size");
+ list<dag> Pattern = [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))];
+ InstrItinClass Itinerary = II_EXT;
+ Format Form = FrmR;
+ string BaseOpcode = instr_asm;
+}
+class EXT_MMR6_DESC : EXT_MMR6_DESC_BASE<"ext", GPR32Opnd, uimm5, MipsExt>;
+
+class PREFE_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
+ RegisterOperand GPROpnd> :
+ CACHE_HINT_MMR6_DESC<instr_asm, MemOpnd, GPROpnd> {
+ string DecoderMethod = "DecodePrefeOpMM";
+}
+class PREFE_MMR6_DESC : PREFE_MMR6_DESC_BASE<"prefe", mem_mm_9, GPR32Opnd>;
+
+class INS_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO, Operand PosOpnd,
+ SDPatternOperator Op = null_frag> : MMR6Arch<instr_asm>,
+ MipsR6Inst {
+ dag OutOperandList = (outs RO:$rt);
+ dag InOperandList = (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src);
+ string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $pos, $size");
+ list<dag> Pattern = [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))];
+ InstrItinClass Itinerary = II_INS;
+ Format Form = FrmR;
+ string BaseOpcode = instr_asm;
+ string Constraints = "$src = $rt";
+}
+class INS_MMR6_DESC : INS_MMR6_DESC_BASE<"ins", GPR32Opnd, uimm5, MipsIns>;
+
+class JALRC_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO> :
+ MMR6Arch<instr_asm>, MipsR6Inst {
+ dag OutOperandList = (outs RO:$rt);
+ dag InOperandList = (ins RO:$dst, RO:$rs);
+ string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
+ list<dag> Pattern = [];
+ InstrItinClass Itinerary = IIBranch;
+ string Constraints = "$dst = $rt";
+ bit isCall = 1;
+ bit hasDelaySlot = 0;
+}
+class JALRC_MMR6_DESC : JALRC_MMR6_DESC_BASE<"jalrc", GPR32Opnd>;
+
//===----------------------------------------------------------------------===//
----------------
As noted in other patches, you don't need to separate *_DESC_BASE from *_DESC if there's only one subclass.
================
Comment at: lib/Target/Mips/MicroMips32r6InstrInfo.td:285-286
@@ +284,4 @@
+class EXT_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO, Operand PosOpnd,
+ SDPatternOperator Op = null_frag> : MMR6Arch<instr_asm>,
+ MipsR6Inst {
+ dag OutOperandList = (outs RO:$rt);
----------------
Indentation
================
Comment at: lib/Target/Mips/MicroMips32r6InstrInfo.td:299
@@ +298,3 @@
+ RegisterOperand GPROpnd> :
+ CACHE_HINT_MMR6_DESC<instr_asm, MemOpnd, GPROpnd> {
+ string DecoderMethod = "DecodePrefeOpMM";
----------------
Indentation
================
Comment at: lib/Target/Mips/MicroMips32r6InstrInfo.td:305-306
@@ +304,4 @@
+class INS_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO, Operand PosOpnd,
+ SDPatternOperator Op = null_frag> : MMR6Arch<instr_asm>,
+ MipsR6Inst {
+ dag OutOperandList = (outs RO:$rt);
----------------
Indentation
================
Comment at: lib/Target/Mips/MicroMips32r6InstrInfo.td:319
@@ +318,3 @@
+class JALRC_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO> :
+ MMR6Arch<instr_asm>, MipsR6Inst {
+ dag OutOperandList = (outs RO:$rt);
----------------
Indentation
================
Comment at: lib/Target/Mips/MicroMipsInstrInfo.td:615
@@ +614,3 @@
+ def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>,
+ ISA_MICROMIPS32R2;
+}
----------------
Indentation (should line up with the first char of MMRel)
================
Comment at: lib/Target/Mips/MipsInstrInfo.td:1501-1504
@@ +1500,6 @@
+let AdditionalPredicates = [NotInMicroMips] in {
+def EXT : MMRel, StdMMR6Rel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>,
+ EXT_FM<0>;
+def INS : MMRel, StdMMR6Rel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>,
+ EXT_FM<4>;
+}
----------------
Indentation
http://reviews.llvm.org/D11798
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