[llvm] r247506 - [x86] enable machine combiner reassociations for 128-bit vector logical integer insts
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Sat Sep 12 07:58:04 PDT 2015
Author: spatel
Date: Sat Sep 12 09:58:04 2015
New Revision: 247506
URL: http://llvm.org/viewvc/llvm-project?rev=247506&view=rev
Log:
[x86] enable machine combiner reassociations for 128-bit vector logical integer insts
Added:
llvm/trunk/test/CodeGen/X86/machine-combiner-int-vec.ll
Modified:
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=247506&r1=247505&r2=247506&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Sat Sep 12 09:58:04 2015
@@ -6408,6 +6408,12 @@ static bool isAssociativeAndCommutative(
case X86::IMUL16rr:
case X86::IMUL32rr:
case X86::IMUL64rr:
+ case X86::PANDrr:
+ case X86::PORrr:
+ case X86::PXORrr:
+ case X86::VPANDrr:
+ case X86::VPORrr:
+ case X86::VPXORrr:
// Normal min/max instructions are not commutative because of NaN and signed
// zero semantics, but these are. Thus, there's no need to check for global
// relaxed math; the instructions themselves have the properties we need.
Added: llvm/trunk/test/CodeGen/X86/machine-combiner-int-vec.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/machine-combiner-int-vec.ll?rev=247506&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/machine-combiner-int-vec.ll (added)
+++ llvm/trunk/test/CodeGen/X86/machine-combiner-int-vec.ll Sat Sep 12 09:58:04 2015
@@ -0,0 +1,68 @@
+; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=sse < %s | FileCheck %s --check-prefix=SSE
+; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=avx < %s | FileCheck %s --check-prefix=AVX
+
+; Verify that 128-bit vector logical ops are reassociated.
+
+define <4 x i32> @reassociate_and_v4i32(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, <4 x i32> %x3) {
+; SSE-LABEL: reassociate_and_v4i32:
+; SSE: # BB#0:
+; SSE-NEXT: paddd %xmm1, %xmm0
+; SSE-NEXT: pand %xmm3, %xmm2
+; SSE-NEXT: pand %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: reassociate_and_v4i32:
+; AVX: # BB#0:
+; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vpand %xmm3, %xmm2, %xmm1
+; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
+
+ %t0 = add <4 x i32> %x0, %x1
+ %t1 = and <4 x i32> %x2, %t0
+ %t2 = and <4 x i32> %x3, %t1
+ ret <4 x i32> %t2
+}
+
+define <4 x i32> @reassociate_or_v4i32(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, <4 x i32> %x3) {
+; SSE-LABEL: reassociate_or_v4i32:
+; SSE: # BB#0:
+; SSE-NEXT: paddd %xmm1, %xmm0
+; SSE-NEXT: por %xmm3, %xmm2
+; SSE-NEXT: por %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: reassociate_or_v4i32:
+; AVX: # BB#0:
+; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vpor %xmm3, %xmm2, %xmm1
+; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
+
+ %t0 = add <4 x i32> %x0, %x1
+ %t1 = or <4 x i32> %x2, %t0
+ %t2 = or <4 x i32> %x3, %t1
+ ret <4 x i32> %t2
+}
+
+define <4 x i32> @reassociate_xor_v4i32(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, <4 x i32> %x3) {
+; SSE-LABEL: reassociate_xor_v4i32:
+; SSE: # BB#0:
+; SSE-NEXT: paddd %xmm1, %xmm0
+; SSE-NEXT: pxor %xmm3, %xmm2
+; SSE-NEXT: pxor %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: reassociate_xor_v4i32:
+; AVX: # BB#0:
+; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vpxor %xmm3, %xmm2, %xmm1
+; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
+
+ %t0 = add <4 x i32> %x0, %x1
+ %t1 = xor <4 x i32> %x2, %t0
+ %t2 = xor <4 x i32> %x3, %t1
+ ret <4 x i32> %t2
+}
+
More information about the llvm-commits
mailing list