[PATCH] D12638: Improve ISel using across lane min/max reduction

[Chad Rosier via llvm-commits]

mcrosier accepted this revision.
mcrosier added a comment.
This revision is now accepted and ready to land.

LGTM with a few nits.


================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:8762
@@ +8761,3 @@
+  if (!isa<ConstantSDNode>(N0.getOperand(1)) ||
+      cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue())
+    return SDValue();
----------------
It might improve readability if we check against != 0.  I.e.,

.. getZExtValue() != 0)

================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:8767
@@ +8766,3 @@
+  if (!isa<ConstantSDNode>(IfTrue.getOperand(1)) ||
+      cast<ConstantSDNode>(IfTrue.getOperand(1))->getZExtValue())
+    return SDValue();
----------------
It might improve readability if we check against != 0.  I.e.,

.. getZExtValue() != 0)

================
Comment at: test/CodeGen/AArch64/aarch64-addv.ll:1
@@ -1,2 +1,2 @@
-; RUN: llc -march=aarch64 < %s | FileCheck %s
+; RUN: llc -march=aarch64 -aarch64-neon-syntax=generic < %s | FileCheck %s
 
----------------
I believe this fix was committed in r246833.  You may need to rebase your patch.


http://reviews.llvm.org/D12638